發(fā)布時(shí)間：2018-04-08 11:38

  本文選題：時(shí)鐘倍頻　切入點(diǎn)：鎖相環(huán)　出處：《北京交通大學(xué)》2017年碩士論文

【摘要】：鎖相技術(shù)在無(wú)線收發(fā)器、傳輸接口、微處理器等領(lǐng)域,有著廣泛的應(yīng)用。包括鎖相環(huán)(Phase-Locked Loop)、串行/解串器(SerDes)、時(shí)鐘與數(shù)據(jù)恢復(fù)(Clock andDataRecovery)電路在內(nèi)的一系列電路的設(shè)計(jì)一直是國(guó)內(nèi)外各高校、研究機(jī)構(gòu)以及企業(yè)研究的熱點(diǎn)。近年來(lái),隨著物聯(lián)網(wǎng)技術(shù)以及半導(dǎo)體技術(shù)的快速發(fā)展,各種微處理器的運(yùn)算能力越來(lái)越強(qiáng),數(shù)字設(shè)備之間的數(shù)據(jù)交換速度越來(lái)越快,如何在提高速度的同時(shí)保障數(shù)據(jù)傳輸?shù)目煽啃?是一個(gè)值得研究的問(wèn)題。在許多應(yīng)用中,高速串行接口已經(jīng)逐漸取代了傳統(tǒng)的并行接口。在高速串行通信接口中常常使用鎖相環(huán)來(lái)產(chǎn)生高頻率的時(shí)鐘信號(hào),但鎖相環(huán)本身的抖動(dòng)積累問(wèn)題增加了輸出時(shí)鐘上的抖動(dòng),限制了數(shù)據(jù)傳輸?shù)乃俣�。延遲鎖定環(huán)(Delay-Locked Loop)具有比鎖相環(huán)更好的抖動(dòng)性能,因此在一些對(duì)時(shí)鐘抖動(dòng)性能要求更高的應(yīng)用中,延遲鎖定環(huán)通常是一個(gè)更好的選擇,但因其無(wú)法像鎖相環(huán)那樣靈活地實(shí)現(xiàn)頻率倍增的功能,它的應(yīng)用受到了一定的限制。本文在對(duì)鎖相環(huán)、延遲鎖定環(huán)這兩種常見(jiàn)鎖相電路進(jìn)行分析與比較的基礎(chǔ)上,介紹了一種將二者優(yōu)勢(shì)相結(jié)合的新型鎖相技術(shù)——倍頻延遲鎖定環(huán)(Multiplying Delay-Locked Loop),它克服了傳統(tǒng)鎖相環(huán)電路存在抖動(dòng)積累的問(wèn)題,同時(shí)保留了其能夠靈活實(shí)現(xiàn)倍頻的特性。隨后,本文對(duì)一種倍頻延遲鎖定環(huán)電路的工作原理和結(jié)構(gòu)進(jìn)行了詳細(xì)地分析,給出了 0.18μm標(biāo)準(zhǔn)CMOS工藝下整體電路從原理圖到版圖的設(shè)計(jì),所設(shè)計(jì)的倍頻延遲鎖定環(huán)的倍頻比為7,可捕獲的輸入?yún)⒖碱l率范圍為 25MHz 到 100MHz。本文的最后,給出了電路的仿真結(jié)果。仿真結(jié)果表明,當(dāng)工藝參數(shù)、電源電壓、溫度在一定范圍內(nèi)變化時(shí),所設(shè)計(jì)的MDLL電路均能穩(wěn)定工作。當(dāng)輸入100MHz的參考時(shí)鐘信號(hào)時(shí),輸出時(shí)鐘頻率為700MHz,抖動(dòng)的峰峰值小于26ps。
[Abstract]:Phase-locked technology has been widely used in wireless transceiver, transmission interface, microprocessor and other fields.The design of a series of circuits including phase-locked loop Phase-Locked Looper serial / demultiplexer SerDesan clock and data recovery circuits has always been a hot research topic in universities research institutions and enterprises at home and abroad.In recent years, with the rapid development of the Internet of things technology and semiconductor technology, the computing power of various microprocessors is becoming stronger and stronger, and the speed of data exchange between digital devices is becoming faster and faster.How to improve the speed and ensure the reliability of data transmission is a problem worth studying.In many applications, high-speed serial interface has gradually replaced the traditional parallel interface.Phase locked loop (PLL) is often used to generate high frequency clock signal in high speed serial communication interface, but the jitter accumulation of PLL itself increases the jitter on the output clock and limits the speed of data transmission.Delay locking loop (Delay-Locked Loop) has better jitter performance than phase-locked loop (PLL), so it is usually a better choice in some applications with higher clock jitter performance.However, its application is limited because it can not realize the function of frequency multiplication as flexibly as PLL.Based on the analysis and comparison of two common phase-locked circuits, the phase-locked loop and the delay-locked loop are analyzed and compared in this paper.This paper introduces a new phase-locking technique, frequency-doubling Delay-Locked locking loop, which combines the advantages of the two techniques. It overcomes the problem of jitter accumulation in the traditional PLL circuit and retains the characteristic that it can realize frequency doubling flexibly.Then, the working principle and structure of a frequency-doubling delay locking loop circuit are analyzed in detail, and the design of the whole circuit from schematic to layout in 0.18 渭 m standard CMOS process is given.The designed double frequency delay locking loop has a frequency doubling ratio of 7 and a trapping reference frequency range of 25MHz to 100 MHz.Finally, the simulation results of the circuit are given.The simulation results show that the designed MDLL circuit can work stably when the process parameters, power supply voltage and temperature change in a certain range.When the reference clock signal of 100MHz is input, the output clock frequency is 700MHz and the peak value of jitter is less than 26ps.
【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN911.8

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