三維集成電路中硅通孔的建模與仿真研究
發(fā)布時間：2018-09-19 19:56
【摘要】：隨著半導體器件特征尺寸不斷接近材料物理極限,漏電流現(xiàn)象和熱問題愈加突出,且隨著互連線尺寸不斷縮小,傳統(tǒng)銅互連的延遲、噪聲和功耗問題愈加嚴重,因而需要發(fā)展三維集成技術來延續(xù)甚至超越摩爾定律。作為三維集成電路的核心技術,硅通孔可實現(xiàn)信號在堆疊層器件間的電學連接,從而縮短互連長度,減小延遲和功耗,縮小芯片占用面積,實現(xiàn)高度集成及異質芯片集成。本論文針對硅通孔開展電路建模研究,發(fā)展準確、快速的電學參數(shù)提取技術,研究硅通孔信號傳輸性能及優(yōu)化方法,相關工作可分為三部分:在第一部分中,研究碳納米管作為硅通孔填充導體材料對電學性能的影響,給出碳納米管填充硅通孔的等效電路模型,結合等效復電導率概念分析信號傳輸性能�？紤]碳納米管中動電感變化所帶來的負面影響,證明將傳統(tǒng)銅材料與碳納米管混合構造新型導體材料,用于填充硅通孔以抑制碳納米管動電感變化對高頻性能穩(wěn)定性的影響。第二部分致力于發(fā)展重布線層中水平互連線及差分硅通孔的寬帶建模方法,給出能夠在直流至100 GHz頻率范圍內(nèi)適用的等效電路模型,并發(fā)展相應的參數(shù)提取技術�；谔岢龅牡刃щ娐纺Ｐ�,研究了設計參數(shù)及溫度變化對電學性能的影響,相關成果對硅通孔的優(yōu)化設計有所幫助。第三部分研究了浮硅基底中硅通孔的寄生電容建模方法,給出了典型三根硅通孔陣列的等效電路模型,結合非線性電容效應分析瞬態(tài)電壓響應。同時還研究了內(nèi)部為浮硅基底的同軸硅通孔,分析設計參數(shù)對非線性電容的影響。研究表明,浮硅基底下的硅通孔同樣可通過在工藝中引入氧化層固定電荷,使硅通孔寄生電容在一定工作電壓范圍內(nèi)穩(wěn)定,從而簡化建模和仿真過程�？傊�,本論文針對三維集成電路中硅通孔進行了一些探索,開展了電路建模和電學特性等方面的研究,得到了一些有益的結果。
[Abstract]:With the characteristic size of semiconductor devices approaching the material physical limit, leakage current phenomenon and thermal problems become more and more prominent, and the delay, noise and power consumption problems of traditional copper interconnection become more and more serious with the decreasing of interconnect size. Therefore, it is necessary to develop three-dimensional integration technology to extend or even exceed Moore's law. As the core technology of 3D integrated circuit, silicon through hole can realize the electrical connection between stacked devices, which can shorten the interconnect length, reduce the delay and power consumption, reduce the occupied area of the chip, and realize the high integration and the heterogeneous chip integration. In this paper, we develop circuit modeling research for silicon through hole, develop accurate and fast electrical parameter extraction technology, study the transmission performance and optimization method of silicon through hole signal. The related work can be divided into three parts: in the first part, The effect of carbon nanotubes (CNTs) on the electrical properties of silicon through porous conductors is studied. The equivalent circuit model of carbon nanotubes filled with silicon through holes is presented. The signal transmission performance is analyzed with the concept of equivalent complex conductivity. Considering the negative effect of dynamic inductance variation in carbon nanotubes, it is proved that a new type of conducting material is constructed by mixing traditional copper materials with carbon nanotubes to fill silicon through holes to suppress the influence of dynamic inductance variation on the stability of high frequency properties of carbon nanotubes. The second part is devoted to the development of broadband modeling method for horizontal interconnects and differential silicon through holes in rewiring layer. The equivalent circuit model which can be used in the frequency range from DC to 100 GHz is given and the corresponding parameter extraction technique is developed. Based on the proposed equivalent circuit model, the effects of design parameters and temperature changes on electrical properties are studied. In the third part, the parasitic capacitance modeling method of silicon through hole in floating silicon substrate is studied. The equivalent circuit model of three typical silicon through hole arrays is given, and the transient voltage response is analyzed with nonlinear capacitance effect. The influence of the design parameters on the nonlinear capacitance is analyzed. The results show that the silicon through hole under the floating silicon substrate can also be stabilized by introducing the fixed charge of the oxide layer in the process, so that the parasitic capacitance of the through hole can be stabilized in a certain working voltage range, thus simplifying the modeling and simulation process. In a word, this thesis has made some exploration on the silicon through hole in 3D integrated circuit, carried out circuit modeling and electrical characteristics, and got some useful results.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN40
本文編號：2251167
[Abstract]:With the characteristic size of semiconductor devices approaching the material physical limit, leakage current phenomenon and thermal problems become more and more prominent, and the delay, noise and power consumption problems of traditional copper interconnection become more and more serious with the decreasing of interconnect size. Therefore, it is necessary to develop three-dimensional integration technology to extend or even exceed Moore's law. As the core technology of 3D integrated circuit, silicon through hole can realize the electrical connection between stacked devices, which can shorten the interconnect length, reduce the delay and power consumption, reduce the occupied area of the chip, and realize the high integration and the heterogeneous chip integration. In this paper, we develop circuit modeling research for silicon through hole, develop accurate and fast electrical parameter extraction technology, study the transmission performance and optimization method of silicon through hole signal. The related work can be divided into three parts: in the first part, The effect of carbon nanotubes (CNTs) on the electrical properties of silicon through porous conductors is studied. The equivalent circuit model of carbon nanotubes filled with silicon through holes is presented. The signal transmission performance is analyzed with the concept of equivalent complex conductivity. Considering the negative effect of dynamic inductance variation in carbon nanotubes, it is proved that a new type of conducting material is constructed by mixing traditional copper materials with carbon nanotubes to fill silicon through holes to suppress the influence of dynamic inductance variation on the stability of high frequency properties of carbon nanotubes. The second part is devoted to the development of broadband modeling method for horizontal interconnects and differential silicon through holes in rewiring layer. The equivalent circuit model which can be used in the frequency range from DC to 100 GHz is given and the corresponding parameter extraction technique is developed. Based on the proposed equivalent circuit model, the effects of design parameters and temperature changes on electrical properties are studied. In the third part, the parasitic capacitance modeling method of silicon through hole in floating silicon substrate is studied. The equivalent circuit model of three typical silicon through hole arrays is given, and the transient voltage response is analyzed with nonlinear capacitance effect. The influence of the design parameters on the nonlinear capacitance is analyzed. The results show that the silicon through hole under the floating silicon substrate can also be stabilized by introducing the fixed charge of the oxide layer in the process, so that the parasitic capacitance of the through hole can be stabilized in a certain working voltage range, thus simplifying the modeling and simulation process. In a word, this thesis has made some exploration on the silicon through hole in 3D integrated circuit, carried out circuit modeling and electrical characteristics, and got some useful results.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN40
【參考文獻】
相關期刊論文 前1條
1 王高峰;趙文生;;三維集成電路中的關鍵技術問題綜述[J];杭州電子科技大學學報;2014年02期
相關博士學位論文 前1條
1 趙文生;三維集成電路中新型互連結構的建模方法與特性研究[D];浙江大學;2013年
，本文編號：2251167
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