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  本文選題：SRAM　切入點(diǎn)：低電壓　出處：《安徽大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：為了滿足人們對高性能電子產(chǎn)品日益增長的需求和降低產(chǎn)品的成本達(dá)到利益的最大化,半導(dǎo)體的制造工藝節(jié)點(diǎn)在持續(xù)的縮小,推動集成電路進(jìn)入后摩爾時代。近年來SOC(片上系統(tǒng))技術(shù)逐漸成為IC設(shè)計業(yè)界的焦點(diǎn),SRAM(靜態(tài)隨機(jī)存取存儲器)作為其必不可少的一部分被集成到SOC芯片中,由于高性能SRAM存儲器存在著不可或缺的應(yīng)用,一直是工業(yè)界和學(xué)術(shù)界研究的熱點(diǎn)。SRAM存儲器主要包括存儲陣列,靈敏放大器,時序控制電路,譯碼電路和輸入輸出驅(qū)動模塊。其中,存儲陣列占據(jù)著整個存儲系統(tǒng)的大部分面積,其性能的優(yōu)劣直接影響著SRAM存儲系統(tǒng)的性能。隨著工藝節(jié)點(diǎn)和電源電壓的下降,器件的閾值電壓越來越小,另外,相鄰晶體管之間閾值電壓的不匹配也越來越明顯,導(dǎo)致SRAM存儲單元的魯棒性越來越差。存儲單元在工作時,讀破壞,半選單元讀破壞越來越頻繁,寫能力也越來越弱,甚至出現(xiàn)讀寫錯誤。SRAM存儲系統(tǒng)的功耗大部分來自單元操作時的動態(tài)功耗和休眠狀態(tài)時的靜態(tài)功耗,隨著工藝節(jié)點(diǎn)的縮小,芯片的靜態(tài)功耗將會越來越大,甚至超過動態(tài)功耗成為芯片的主要功耗。電壓的下降可以顯著地降低靜態(tài)功耗和二次方形式的降低動態(tài)功耗,低電壓下SRAM的設(shè)計越來越普遍,在保證單元性能的前提下,可以很好的延長便攜式設(shè)備的電池壽命。但低電壓下,SRAM單元的性能進(jìn)一步的惡化,如速度的下降,穩(wěn)定性的惡化,錯誤率的飆升等;這些,使得傳統(tǒng)SRAM單元越來越不能滿足我們的需求。本文首先分析研究了 SRAM存儲系統(tǒng)的重要性及先進(jìn)工藝下SRAM單元性能面臨的各種挑戰(zhàn)。其次在分析傳統(tǒng)SRAM存儲單元工作原理的基礎(chǔ)上,采用VTC蝴蝶曲線,字線電壓驅(qū)動,位線電壓驅(qū)動和N曲線方法衡量了其靜態(tài)噪聲容限。在這種背景下,分析研究了前人提出的多種單元優(yōu)化方法。這些設(shè)計方法,大部分僅僅優(yōu)化了單元讀、寫一方面的性能,另一方面保持不變或者有惡化的趨勢;單端讀寫單元往往惡化了讀寫速度,并使靈敏放大器的設(shè)計面臨挑戰(zhàn);輔助電路的設(shè)計,往往會使SRAM的設(shè)計復(fù)雜化。為了使SRAM存儲單元的性能得到整體的提升,本文提出了讀寫裕度同時提升的新型10TSARM單元電路結(jié)構(gòu),可以很大程度上抑制傳統(tǒng)6T存儲單元讀操作時"0"節(jié)點(diǎn)的分壓問題,提高SRAM存儲單元的讀靜態(tài)噪聲容限(RSNM),進(jìn)而提升SRAM存儲單元的讀穩(wěn)定性。在寫操作時,用位線電壓提供交叉耦合反相器的電源電壓,降低了單元維持"1"的能力和一邊反相器的翻轉(zhuǎn)點(diǎn),這樣可以很大程度的提高SRAM存儲單元的寫裕度(WM)。同時,可以優(yōu)化SRAM存儲單元的抗PVT波動能力,并且可以降低SRAM存儲單元的最小操作電壓�；�于SMIC 28nm工藝節(jié)點(diǎn)仿真結(jié)果顯示,新型10T單元結(jié)構(gòu)在電源電壓為1.05V時,和傳統(tǒng)6T單元相比,RSNM提升了 2.19倍,WM提升了 2.13倍。同時,在單元讀寫操作時,錯誤率較低。另外,新型單元的最小工作電壓僅為傳統(tǒng)的59.19%,擁有更好的抗工藝變化能力。
[Abstract]:In order to meet the people of high performance electronic products growing demand and reduce the cost of the product to achieve the maximum benefit of the semiconductor manufacturing process, the nodes in the continue to shrink, to promote the integrated circuit after entering the Moore era. In recent years, SOC (system on chip) technology has gradually become the focus of IC design industry, SRAM (static random access memory) as part of its essential is integrated into the SOC chip, the high performance SRAM memory has an application,.SRAM memory has been a hot topic in industrial and academic research mainly includes memory array, sense amplifier, a timing control circuit, decoding circuit and input and output drive module. The storage array occupies the most the area of the storage system, its performance will directly affect the performance of SRAM storage system. With the decline process node and the supply voltage is. More and more small pieces of the threshold voltage, the threshold voltage mismatch between adjacent transistors is becoming more and more obvious, leading to robust SRAM memory cell is getting worse. The storage unit failure at work, read, read half unit failure more frequently, writing ability is more and more weak, even the power of reading and writing the error of.SRAM storage system mostly from static power consumption dynamic power unit operation and a dormant state, as the technology node shrink, the static power consumption will be more and more big chip, even more than the dynamic power consumption has become the main power chip. The voltage drop can significantly reduce the static power consumption and the two party in the form of reducing dynamic power consumption low voltage design, SRAM is more and more common, under the premise of ensuring unit performance, can be very good to prolong the battery life of portable devices. But under low voltage, the performance of SRAM unit in The deterioration of a step, such as the speed of the decline, stability deteriorated, error rate soared; of these, the traditional SRAM unit can not meet the growing demand. We study the various challenges facing the unit performance of SRAM importance SRAM storage system and advanced technology this paper analyzes. Secondly based on the analysis of traditional SRAM storage the working principle of the unit, the VTC butterfly curve, word line voltage, bit line voltage drive and N curve method to measure the static noise margin. In this context, analysis of the multiple unit optimization method proposed by previous researchers. Most of these design methods, optimization of the unit only read and write performance on the one hand on the other hand, remain unchanged or have a tendency to deteriorate; single ended read and write unit often deteriorates the read and write speed, and make the design of sensitive amplifier challenges; auxiliary circuit design, often make the SRAM The design is complex. In order to make the performance of the SRAM storage unit to get the whole promotion, is proposed in this paper to read and write margin and improve the new 10TSARM unit circuit structure, can greatly inhibit the traditional 6T storage unit read "0" node pressure, improve the read static noise margin SRAM storage unit (RSNM), and thus enhance the stability of the SRAM storage unit. Read in write operation, a bit line voltage supply voltage of cross coupled inverters, reduces the turning point unit maintain "1" ability and side inverter, which can greatly improve the SRAM storage unit and write margin (WM) at the same time. PVT, anti wave ability can optimize the SRAM storage unit, the minimum operating voltage and can reduce the SRAM storage unit. SMIC 28nm technology node based simulation results show that the new 10T cell structure in the power supply voltage of 1.05V, and Compared with the 6T unit, the RSNM increased by 2.19 times and the WM increased by 2.13 times. At the same time, the error rate of the cell read and write operation is low. Moreover, the minimum working voltage of the new cell is only 59.19% of the traditional one, and has a better ability to resist technological change.

【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP333

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本文編號：1580387