發(fā)布時間：2018-05-30 16:43

  本文選題：CMOS測試平臺 + FPGA��； 參考：《大連理工大學(xué)》2016年碩士論文

【摘要】：CMOS圖像傳感器產(chǎn)業(yè)進(jìn)入快速發(fā)展期,傳感器的測試對于產(chǎn)品的研發(fā)生產(chǎn)至關(guān)重要,而國內(nèi)可借鑒的完整的測試方案極少,國外主流的圖像傳感器測試機(jī)成本又極高�；�于這種現(xiàn)狀,本文設(shè)計(jì)了一款基于FPGA與USB3.0接口的CMOS圖像傳感器測試平臺。平臺承擔(dān)了B1000和B4000兩款CMOS傳感器測試任務(wù),且平臺可擴(kuò)展性強(qiáng),并能以較小代價兼容更多未知類型CMOS圖像傳感器。系統(tǒng)硬件為插針拼接式結(jié)構(gòu),測試不同的傳感器時更換不同的傳感器圖像采集電路與傳輸主板進(jìn)行連接。傳輸主板以FPGA作主控,采用DDR2 SDRAM作為高速緩存,采用USB3.0芯片作為數(shù)據(jù)傳輸口。兩個子板接口統(tǒng)一為B4000接口模式,B1000傳感器的傳感器驅(qū)動時序產(chǎn)生以及數(shù)據(jù)接收是在其傳感器采集子板上進(jìn)行,然后子板主控FPGA模擬B4000接口與主板進(jìn)行通信。系統(tǒng)軟件分三部分：高速傳輸主板FPGA程序,B1000子板FPGA程序和PC端程序。主板程序采用VHDL編寫,涉及PC端指令的解析、高速LVDS數(shù)據(jù)接收和并行化、圖像還原、位寬變換、DDR2 SDRAM驅(qū)動以及USB3.0芯片驅(qū)動；B1000子板采用Verilog HDL編寫,涉及芯片驅(qū)動時序產(chǎn)生以及對B4000圖像格式與控制總線的模擬；PC端程序采用C/C++編寫,采用Cypress官方API實(shí)現(xiàn)底層通信,采用MFC類庫進(jìn)行界面開發(fā)。實(shí)現(xiàn)了圖像數(shù)據(jù)的實(shí)時接收顯示、傳感器寄存器的讀寫、圖像的導(dǎo)出和回放等功能。經(jīng)測試,單獨(dú)USB3.0芯片傳輸速率為318MB/s,單獨(dú)DDR2 SDRAM傳輸速率為310MB/s,系統(tǒng)整體接口傳輸速率277MB/s,實(shí)現(xiàn)了傳感器圖像全幀全幅的實(shí)時傳輸。系統(tǒng)指令總線與數(shù)據(jù)總線信道均穩(wěn)定無誤碼,實(shí)現(xiàn)了預(yù)定設(shè)計(jì)要求。本設(shè)計(jì)為CMOS圖像傳感器的測試提供了一種參考方案,有很強(qiáng)的應(yīng)用價值。
[Abstract]:CMOS image sensor industry has entered a period of rapid development, sensor testing is very important for product development and production, but there are very few complete testing schemes available in China, and the cost of mainstream image sensor testing machines abroad is extremely high. Based on this situation, this paper designs a CMOS image sensor testing platform based on FPGA and USB3.0 interface. The platform takes on the task of testing B1000 and B4000 CMOS sensors, and the platform is extensible and can be compatible with more unknown CMOS image sensors at a lower cost. The hardware of the system is a pin splicing structure. When testing different sensors, different sensor image acquisition circuits are replaced to connect with the transmission motherboard. The main board uses FPGA as main control, DDR2 SDRAM as cache and USB3.0 chip as data transmission port. The two sub-board interfaces are unified into the B4000 interface mode and the sensor driver timing generation and data reception are carried out on the sensor acquisition sub-board, and then the sub-board master control FPGA simulates the B4000 interface to communicate with the main board. System software is divided into three parts: high-speed transmission motherboard FPGA program B 1000 sub-board FPGA program and PC program. The main board program is written with VHDL, which involves the analysis of PC side instructions, high-speed LVDS data receiving and parallelization, image restoration, bit width conversion DDR2 SDRAM driver and USB3.0 chip driver B1000 subboard written by Verilog HDL. The analog PC program of B4000 image format and control bus is written by C / C, Cypress official API is used to realize bottom communication, and MFC class library is used to develop interface. The functions of real-time receiving and displaying of image data, reading and writing of sensor register, export and playback of image are realized. The test results show that the transmission rate of single USB3.0 chip is 318MB / s, that of single DDR2 SDRAM is 310MB / s, and that of the whole system interface is 277MB / s. The system instruction bus and data bus channel are stable and correct code, and the predetermined design requirements are achieved. This design provides a reference scheme for the test of CMOS image sensor and has strong application value.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP212

【參考文獻(xiàn)】

相關(guān)期刊論文 前9條

1 孫波;王曉艷;;CCD圖像傳感器和CMOS圖像傳感器的比較研究[J];信息通信;2015年12期

2 張文超;黃善勇;曾小東;;基于FPGA高速數(shù)據(jù)傳輸?shù)谋忍刈孕Ｕ�技術(shù)[J];無線電工程;2011年11期

3 李大鵬;徐東明;陳文宣;;基于門延時的數(shù)字TDC電路設(shè)計(jì)[J];中國集成電路;2011年07期

4 王旭東;葉玉堂;;CMOS與CCD圖像傳感器的比較研究和發(fā)展趨勢[J];電子設(shè)計(jì)工程;2010年11期

5 黃美玲;張伯珩;邊川平;李露瑤;達(dá)選福;;CCD和CMOS圖像傳感器性能比較(英文)[J];科學(xué)技術(shù)與工程;2007年02期

6 吳昱e，

本文編號：1956001