本文選題：FPGA + QC-LDPC　； 參考：《北京交通大學》2014年碩士論文

【摘要】：摘要：信道編碼一直以來就是通信屆研究的一個熱點,自從LDPC碼問世以來,一直成為人們研究的熱點,LDPC碼具有靈活的校驗矩陣構造、良好的糾錯性能而且譯碼復雜度低、譯碼吞吐率高的特點。隨著無線局域網技術,超大光纖容量的發(fā)展,在信道上為了使信息能夠更準確的傳輸,對信道編碼技術要求很高。如今LDPC碼被IEEE802.11n標準采納為信道編碼的一種方案,并且在未來的第四代OFDM通信系統(tǒng)中得到廣泛應用。本文正是在IEEE802.11n的標準下,以FPGA為開發(fā)平臺采用準循環(huán)的編碼結構來設計編譯碼器。準循環(huán)QC-LDPC碼具有良好的糾錯性能以及便于用硬件實現,目前LDPC碼譯碼算法種類較多,本文在研究各種譯碼算法的基礎上,選擇了一種最佳的譯碼算法作為研究對象,并且用Xilinx公司開發(fā)的FPGA芯片對算法進行驗證。主要工作如下： 首先,介紹LDPC碼的相關背景知識以及LDPC編碼和譯碼的基本原理以及FPGA開發(fā)技術。其次,在確定了校驗矩陣之后要確定編譯碼的算法,在matlab環(huán)境下建立仿真模型,對編譯碼的性能做出分析,選定最佳的設計算法。同時算法設計完成之后確定一個用于FPGA的設計方案,將其在ISE14.1開發(fā)工具下用verilog語言對編譯碼的算法進行功能仿真,最后將整個系統(tǒng)進行綜合在FPGA開發(fā)板上做驗證,將譯碼器的輸出結果與matlab的譯碼結果作對比,以便得出結論設計實現結果表明,譯碼器在時序、資源占用以及性能上滿足系統(tǒng)要求。
[Abstract]:Absrtact: Channel coding has always been a hot topic in the field of communication. Since the advent of LDPC codes, it has been a hot research topic. It has flexible construction of check matrix, good error-correcting performance and low decoding complexity. High throughput in decoding. With the development of wireless local area network (WLAN) technology and large fiber capacity, channel coding technology is required in order to transmit information more accurately on the channel. Now LDPC code is adopted as a channel coding scheme by IEEE802.11n standard, and it is widely used in the fourth generation OFDM communication system in the future. In this paper, based on the standard of IEEE802.11n, the quasi-cyclic coding structure is adopted to design the codec based on FPGA. Quasi-cyclic QC-LDPC codes have good error-correcting performance and are easy to implement in hardware. At present, there are many kinds of decoding algorithms for LDPC codes. Based on the study of various decoding algorithms, this paper selects an optimal decoding algorithm as the research object. The algorithm is verified by FPGA chip developed by Xilinx Company. The main tasks are as follows: Firstly, the background of LDPC code, the basic principle of LDPC coding and decoding, and the FPGA development technology are introduced. Secondly, after determining the check matrix, the algorithm of encoding and decoding should be determined, and the simulation model should be established in matlab environment, the performance of encoding and decoding should be analyzed, and the best design algorithm should be selected. At the same time, after the algorithm design is completed, a design scheme for FPGA is determined, which is simulated by verilog language under the ISE14.1 development tool. Finally, the whole system is synthesized on the FPGA development board to verify. The output of the decoder is compared with the decoding result of matlab, and the design and implementation results show that the decoder meets the requirements of the system in timing, resource occupation and performance.
【學位授予單位】：北京交通大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN911.22

【參考文獻】

相關期刊論文 前2條

1 李千玲;陳偉;樊豐;;基于DVB-T2標準的LDPC碼最小和譯碼算法的改進[J];電視技術;2011年05期

2 張靖琳;劉榮科;趙嶺;;高碼率LDPC碼譯碼器的優(yōu)化設計與實現[J];電子與信息學報;2009年01期

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本文編號：1847341