發(fā)布時(shí)間：2018-07-15 13:52

【摘要】：高速發(fā)展的處理器技術(shù)已經(jīng)發(fā)生了革命性的變化，多核處理器逐漸代替單核處理器成為處理器技術(shù)主流。作為通用微處理器的一個(gè)分支，數(shù)字信號(hào)處理器即DSP也跨進(jìn)了以多核，尤其是異構(gòu)多核DSP為主導(dǎo)的高速發(fā)展時(shí)代。 嵌入式異構(gòu)多核DSP處理器是軟硬件協(xié)同設(shè)計(jì)的面向應(yīng)用的專用微處理器。從應(yīng)用角度而言，提升用戶體驗(yàn)的努力不僅僅體現(xiàn)在升級(jí)操作系統(tǒng)，，更在于開(kāi)發(fā)更合適的硬件機(jī)制。任務(wù)調(diào)度是操作系統(tǒng)和硬件系統(tǒng)需要共同關(guān)注的環(huán)節(jié)。異構(gòu)多核處理器體系結(jié)構(gòu)的出現(xiàn)為任務(wù)調(diào)度問(wèn)題帶來(lái)了新的變化，如何設(shè)計(jì)能夠有效實(shí)現(xiàn)任務(wù)調(diào)度的硬件機(jī)制來(lái)支撐任務(wù)調(diào)度算法實(shí)現(xiàn)，使異構(gòu)多核處理器系統(tǒng)能夠充分發(fā)揮性能已經(jīng)成為亟待解決的問(wèn)題。在嵌入式異構(gòu)多核DSP處理器操作系統(tǒng)中，多核任務(wù)的調(diào)度根據(jù)多核任務(wù)調(diào)度算法實(shí)現(xiàn)。而多核任務(wù)調(diào)度的算法運(yùn)作實(shí)際上是通過(guò)調(diào)用調(diào)度機(jī)制的驅(qū)動(dòng)程序，從而驅(qū)動(dòng)底層硬件運(yùn)作的過(guò)程。在整個(gè)任務(wù)調(diào)度機(jī)制中，底層的硬件是基礎(chǔ)，驅(qū)動(dòng)程序是支撐。 本文以國(guó)防科技大學(xué)計(jì)算機(jī)學(xué)院研制的高性能異構(gòu)五核XDSP設(shè)計(jì)工程為背景，為XDSP設(shè)計(jì)了能夠有效支持多核任務(wù)調(diào)度的底層硬件機(jī)制和配套的驅(qū)動(dòng)程序，是XDSP多核系統(tǒng)能夠順利運(yùn)行并發(fā)揮其性能的保障。本文主要完成了以下工作： 基于XDSP的體系結(jié)構(gòu)特點(diǎn)和豐富的片上資源，為XDSP設(shè)計(jì)了硬件調(diào)度機(jī)制，實(shí)現(xiàn)了MCU子系統(tǒng)和DSP子系統(tǒng)間的數(shù)據(jù)通信和MCU對(duì)DSP子系統(tǒng)的控制； 配合XDSP多核調(diào)度的硬件機(jī)制，設(shè)計(jì)了配套的驅(qū)動(dòng)程序，包括多種BOOT模式下的BOOT程序，實(shí)施調(diào)度和任務(wù)同步的交叉中斷處理程序等，為調(diào)度機(jī)制的運(yùn)行提供了驅(qū)動(dòng)支撐； 分別在模塊級(jí)和系統(tǒng)級(jí)對(duì)調(diào)度機(jī)制進(jìn)行了模擬功能驗(yàn)證，驗(yàn)證中組合使用了覆蓋率驅(qū)動(dòng)的驗(yàn)證方法，基于斷言的驗(yàn)證方法和軟硬件協(xié)同仿真等驗(yàn)證方法； 實(shí)現(xiàn)了XDSP的FPGA原型設(shè)計(jì)，對(duì)調(diào)度機(jī)制進(jìn)行了較全面的系統(tǒng)級(jí)仿真驗(yàn)證，并據(jù)此實(shí)現(xiàn)了JPEG解碼程序在XDSP上的任務(wù)分派和調(diào)度。
[Abstract]:The rapid development of processor technology has undergone a revolutionary change, multi-core processors have gradually replaced single-core processors into the mainstream of processor technology. As a branch of universal microprocessor, DSP (Digital signal processor) has also stepped into the era of high speed development with multi-core, especially heterogeneous multi-core DSP. Embedded heterogeneous multi-core DSP processor is an application-oriented microprocessor which is codesigned by hardware and software. From an application point of view, efforts to enhance the user experience are not only reflected in upgrading the operating system, but also in developing more appropriate hardware mechanisms. Task scheduling is a link that the operating system and hardware system need to pay attention to. The emergence of heterogeneous multi-core processor architecture has brought new changes to the task scheduling problem. How to design a hardware mechanism that can effectively implement task scheduling to support the implementation of task scheduling algorithm. It has become an urgent problem to make heterogeneous multi-core processor system give full play to its performance. In embedded heterogeneous multi-core DSP processor operating system, the scheduling of multi-core tasks is based on multi-core task scheduling algorithm. The algorithm operation of multi-core task scheduling is actually the process of driving the underlying hardware operation by calling the driver of the scheduling mechanism. In the whole task scheduling mechanism, the underlying hardware is the foundation and the driver is the support. Based on the design engineering of high performance heterogeneous five-core XDSP developed by computer School of National University of National Defense Science and Technology, this paper designs the underlying hardware mechanism and supporting driver for XDSP, which can effectively support multi-core task scheduling. It is the guarantee that XDSP multi-core system can run smoothly and give full play to its performance. The main work of this paper is as follows: based on the architecture characteristics of XDSP and abundant on-chip resources, the hardware scheduling mechanism is designed for XDSP, the data communication between MCU subsystem and DSP subsystem is realized and MCU controls DSP subsystem; With the hardware mechanism of XDSP multi-core scheduling, a complete set of drivers is designed, including the boot program in various boot modes, the cross-interrupt processing program for scheduling and task synchronization, and so on. It provides driving support for the operation of the scheduling mechanism, and simulates the scheduling mechanism at the module level and the system level, and combines the coverage driven verification method in the verification. The verification methods based on assertion and hardware / software co-simulation are implemented, the FPGA prototype design of XDSP is implemented, and the scheduling mechanism is verified by system-level simulation. Based on this, the task assignment and scheduling of JPEG decoding program on XDSP are realized.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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