發(fā)布時(shí)間：2018-06-12 22:29

  本文選題：低功耗設(shè)計(jì) + SRAM�。� 參考：《安徽大學(xué)》2012年碩士論文

【摘要】：近年來(lái),以智能手機(jī)和平板電腦為代表的大量移動(dòng)設(shè)備的應(yīng)用增長(zhǎng)迅速,但其普遍存在發(fā)熱量過(guò)大和電池續(xù)航時(shí)間短的問(wèn)題,這就給嵌入式芯片的低功耗設(shè)計(jì)帶來(lái)嚴(yán)重的挑戰(zhàn)。由于靜態(tài)隨機(jī)存儲(chǔ)器(SRAM)在系統(tǒng)芯片(SoC)上的容量越來(lái)越大,SRAM所占的功耗在整個(gè)芯片中的比例也在不斷上升,迫切需要解決SRAM的功耗問(wèn)題。傳統(tǒng)的方法是伴隨著工藝的進(jìn)步,同時(shí)降低電源電壓(VDD)和閾值電壓(Vth)的方法來(lái)滿(mǎn)足性能和功耗要求,但逐漸增長(zhǎng)的亞閾值和柵漏流限制了這種降低,所以現(xiàn)在需要采用新的低功耗策略。 降低電源電壓到閾值電壓以下的設(shè)計(jì),即亞閾值設(shè)計(jì)成為了一種潛在的低功耗應(yīng)用技術(shù),且被大量設(shè)計(jì)所證實(shí)。降低電源電壓會(huì)使功耗成平方下降,但其會(huì)導(dǎo)致性能損失,然而在許多應(yīng)用場(chǎng)景中,例如待機(jī)狀態(tài)以及某些對(duì)性能要求不高的產(chǎn)品中,其中包括傳感器和醫(yī)療芯片等,這種性能損失是可以接受的。因此,亞閥值的SRAM設(shè)計(jì)成為了解決系統(tǒng)存儲(chǔ)器能耗的一個(gè)有效措施。 進(jìn)入亞閾值區(qū)后,SRAM的設(shè)計(jì)面臨了很大的挑戰(zhàn)。由于亞閥值器件電流與電源電壓和閡值電壓成指數(shù)關(guān)系,導(dǎo)致亞閾值電路的延時(shí)也與VDD和Vth成指數(shù)關(guān)系,這就導(dǎo)致了電路的性能對(duì)工藝波動(dòng)、電源電壓噪聲以及溫度變化(PVT)的極度敏感性。例如一個(gè)小的Vth波動(dòng),特別是由于工藝的隨機(jī)摻雜波動(dòng)(RDF)導(dǎo)致的Vth波動(dòng),會(huì)帶來(lái)較大的延時(shí)波動(dòng),可能使電路的功能發(fā)生錯(cuò)誤,降低了系統(tǒng)的良率。本文針對(duì)亞閾值SRAM受PVT波動(dòng)的影響,主要研究了亞閾值SRAM的PVT波動(dòng)檢測(cè)與補(bǔ)償設(shè)計(jì)。主要的研究?jī)?nèi)容包括如下： (1)常規(guī)超閾值電路設(shè)計(jì)中的PVT波動(dòng)影響,分析了其中采用的波動(dòng)檢測(cè)方法和后續(xù)的各種補(bǔ)償方法： (2)亞閾值SRAM設(shè)計(jì)所遇到的挑戰(zhàn),重點(diǎn)研究了其中的關(guān)鍵電路,如存儲(chǔ)單元和靈敏放大器的設(shè)計(jì),并提出了本文的亞閾值SRAM設(shè)計(jì)： (3)針對(duì)亞閾值SRAM受PVT波動(dòng)的影響,本文創(chuàng)新地提出了基于其讀取延時(shí)波動(dòng)檢測(cè)和后續(xù)電源電壓調(diào)節(jié)的補(bǔ)償設(shè)計(jì)方法。 首先,本文構(gòu)造了亞閾值SRAM的一個(gè)延時(shí)關(guān)鍵路徑電路,利用這個(gè)電路的工作狀態(tài)來(lái)反映PVT波動(dòng)對(duì)亞閾值SRAM讀取延時(shí)的影響,然后利用延時(shí)檢測(cè)電路,對(duì)位線(xiàn)壓差建立延時(shí)進(jìn)行檢測(cè),根據(jù)檢測(cè)結(jié)果,通過(guò)編碼電路給出不同的補(bǔ)償信息,最后利用低壓差線(xiàn)性穩(wěn)壓器(LDO)來(lái)實(shí)現(xiàn)全局的電源電壓調(diào)節(jié)以補(bǔ)償PVT的波動(dòng),并構(gòu)成一個(gè)自適應(yīng)調(diào)節(jié)系統(tǒng)。 通過(guò)對(duì)亞閾值SRAM以及PVT波動(dòng)檢測(cè)和補(bǔ)償電路在不同工藝角的實(shí)驗(yàn)發(fā)現(xiàn),采用本文設(shè)計(jì)后,在較好工藝角下,PVT檢測(cè)和LDO補(bǔ)償電路的輸出電源電壓最終穩(wěn)定在300mV上,即亞閾值SRAM工作在最低的電源電壓下,實(shí)現(xiàn)超低能耗的穩(wěn)定工作；而在最差SNSP (Slow NMOS Slow PMOS)工藝角下,最終電源電壓穩(wěn)定在375mV,也可以實(shí)現(xiàn)在最差工藝角下的穩(wěn)定工作；另外當(dāng)溫度從-20-100℃之間波動(dòng)時(shí),采用本文的設(shè)計(jì)后,讀取延時(shí)平均減小了64.4%,標(biāo)準(zhǔn)差僅為未采用本文設(shè)計(jì)電路的17.3%,有效地緩解了亞閾值SRAM延時(shí)受PVT波動(dòng)的影響,縮短了讀取周期時(shí)間；同時(shí)每周期平均能耗僅為未采用補(bǔ)償電路的24.34%,而PVT電路本身帶來(lái)的額外能耗僅為4.38%,提高了能耗利用率。
[Abstract]:In recent years, a large number of mobile devices, such as smartphones and tablet computers, have grown rapidly, but there is a widespread problem of excessive heating and short battery life, which poses a serious challenge to the low power design of embedded chips. The capacity of the static random memory (SRAM) on the system chip (SoC) is becoming more and more important. Large, the proportion of SRAM's power consumption in the whole chip is also rising, and it is urgent to solve the power consumption problem of SRAM. The traditional method is with the progress of the technology, while reducing the power supply voltage (VDD) and the threshold voltage (Vth) method to meet the performance and power requirements, but the increasing subthreshold and gate drain limit the reduction of this reduction. So now we need to adopt a new low power strategy.
The design of reducing the power supply voltage to the threshold voltage, that is, the subthreshold design becomes a potential low power application technology and is proved by a large number of designs. Reducing the power supply voltage will reduce the power consumption to the square, but it can cause performance loss, however, in many applications, such as standby state and some performance requirements are not high. In the product, including sensors and medical chips, this performance loss is acceptable. Therefore, the subthreshold SRAM design is an effective measure to understand the energy consumption of system memory.
After entering the subthreshold region, the design of SRAM faces great challenges. As the sub threshold device current is exponentially related to the power supply voltage and threshold voltage, the delay of the subthreshold circuit is also exponentially related to the VDD and Vth, which leads to the extreme sensitivity of the circuit performance to the process fluctuation, the power supply voltage noise and the temperature change (PVT). For example, a small Vth fluctuation, especially the Vth fluctuation caused by the random dopant fluctuation (RDF) of the process, will bring large delay fluctuation, which may make the function of the circuit error and reduce the good rate of the system. This paper mainly studies the PVT wave detection and compensation design of subthreshold SRAM for the influence of the PVT fluctuation in subthreshold SRAM. The main contents of the study include the following:
(1) the influence of PVT fluctuation in conventional super threshold circuit design, and the wave detection methods and subsequent compensation methods adopted are analyzed.
(2) the challenge of the subthreshold SRAM design, focusing on the key circuits, such as the design of the storage unit and the sensitive amplifier, and the subthreshold SRAM design in this paper.
(3) in view of the influence of PVT fluctuation on subthreshold SRAM, this paper proposes a compensation design method based on its read delay ripple detection and subsequent power supply voltage regulation.
First, a time-delay critical path circuit of subthreshold SRAM is constructed, which uses the working state of the circuit to reflect the effect of PVT fluctuation on the reading delay of the sub threshold SRAM. Then the delay detection circuit is used to detect the delay of the bit line pressure difference, and the different compensation information is given by the coding circuit according to the detection results. The low voltage differential linear regulator (LDO) is used to realize the global power supply voltage regulation to compensate for the fluctuation of PVT, and form an adaptive regulation system.
Through the experiments of subthreshold SRAM and PVT wave detection and compensation circuit in different process angles, it is found that the output voltage of PVT detection and LDO compensation circuit is finally stabilized on 300mV, that is, subthreshold SRAM works under the lowest electric source voltage to achieve the stability of ultra low energy consumption. At the worst SNSP (Slow NMOS Slow PMOS) process angle, the ultimate power supply voltage is stable at 375mV and can also achieve stable work at the worst process angle. In addition, when the temperature fluctuates from -20-100 C, the average reading delay is reduced by 64.4%, and the standard difference is only 17.3% of the design circuit. The delay of the subthreshold SRAM is affected by the fluctuation of PVT, and the reading cycle time is shortened. At the same time, the average energy consumption per cycle is only 24.34% of the compensation circuit, and the additional energy consumption of the PVT circuit itself is only 4.38%, which improves the utilization of energy consumption.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP333;TN47

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