氧化鋅薄膜晶體管的模擬研究
發(fā)布時(shí)間：2018-10-05 13:28
【摘要】：隨著信息時(shí)代的發(fā)展,在顯示技術(shù)領(lǐng)域中,有源驅(qū)動(dòng)平板顯示技術(shù)的發(fā)展越來越廣泛和深入。薄膜晶體管(Thin-film Transistor,TFT)作為有源矩陣液晶顯示器件(AMLCD)的重要元件,也得到了廣泛的關(guān)注。氧化鋅薄膜晶體管(Zn O TFT)因具有遷移率高、適于低溫生產(chǎn)、透光性好等優(yōu)點(diǎn)在柔性和透明電子學(xué)中具有廣泛的應(yīng)用前景。Zn O TFT不僅能夠解決硅基TFT不透明、光敏性差、制備工藝復(fù)雜的問題,還有效地避免了有機(jī)薄膜晶體管載流子遷移率低、功耗高的現(xiàn)象。因此,越來越多的機(jī)構(gòu)開始了對(duì)Zn O TFT的研究歷程。隨著集成電路的高速發(fā)展,依靠工藝流片的方式進(jìn)行工藝級(jí)的條件設(shè)計(jì)和優(yōu)化是絕對(duì)不可能的,因此,實(shí)現(xiàn)集成電路加工工藝過程的數(shù)字化模擬和仿真勢(shì)在必行。然而,到目前為止,關(guān)于氧化鋅薄膜晶體管的研究工作主要集中在制備工藝上,器件建模的卻很有限。本文主要對(duì)雙柵Zn O TFT進(jìn)行了建模和器件仿真,模型基于其他課題組已提出的禁帶中央高斯分布的深能級(jí)缺陷態(tài)以及呈指數(shù)分布的帶尾態(tài)缺陷態(tài)模型。首先對(duì)雙柵Zn O TFT的三種工作模式進(jìn)行了對(duì)比,最終確定采用頂柵-底柵短路工作模式進(jìn)行接下來的研究,接著研究了深能級(jí)和帶尾態(tài)缺陷態(tài)對(duì)器件性能的影響,還有源漏電極位置及厚度對(duì)器件性能的影響。結(jié)果表明,帶尾態(tài)缺陷態(tài)主要影響器件的開態(tài)特性,深能級(jí)則對(duì)開啟電壓影響較大;源漏電極頂接觸的器件特性優(yōu)于底接觸。在以上基礎(chǔ)上提出了雙柵復(fù)合介質(zhì)Zn O TFT,柵絕緣層使用Si O2-Hf O2-Si O2夾心結(jié)構(gòu),通過對(duì)比雙柵單介質(zhì)Zn O TFT和雙柵復(fù)合介質(zhì)Zn O TFT性能發(fā)現(xiàn)雙柵復(fù)合介質(zhì)Zn O TFT性能更加優(yōu)越。從溝道中載流子分布、溝道能帶圖分布、晶界勢(shì)壘高度Vb的變化以及溝道中電場(chǎng)、電勢(shì)的分布等方面對(duì)器件性能的改善機(jī)理進(jìn)行了研究。對(duì)采用高k材料的薄膜晶體管的影響因素進(jìn)行了研究,高k材料介電常數(shù)越大,器件性能越好;高k材料膜厚越小、在絕緣層中所占比重越大,器件性能越好;采用不同high-k材料時(shí),柵極對(duì)溝道的控制作用也不一樣。最后,還研究了晶界勢(shì)壘高度Vb的變化與閾值電壓之間的關(guān)系,得出Vb最大時(shí)所對(duì)應(yīng)的VGS與仿真所抽取的閾值電壓基本一致的結(jié)論。
[Abstract]:With the development of information age, the development of active drive flat panel display technology is more and more extensive in the field of display technology. Thin film transistor (Thin-film Transistor,TFT), as an important component of active matrix liquid crystal display (AMLCD), has been paid more and more attention. Zinc oxide thin film transistor (Zn O TFT) has a wide application prospect in flexible and transparent electronics because of its high mobility, suitable for low temperature production and good transmittance. Zno TFT can not only solve the opacity of silicon based TFT, but also have poor Guang Min property. The complex preparation process effectively avoids the phenomenon of low carrier mobility and high power consumption in organic thin film transistors. Therefore, more and more institutions began to study the course of Zn O TFT. With the rapid development of integrated circuit, it is absolutely impossible to design and optimize the process level condition by the way of process flow sheet. Therefore, it is imperative to realize the digital simulation and simulation of integrated circuit processing process. However, so far, the research on ZnO thin film transistors is mainly focused on the fabrication process, but the device modeling is very limited. In this paper, the modeling and device simulation of double-gate Zn O TFT are mainly carried out. The model is based on the deep level defect state in the center Gao Si distribution of the forbidden band and the defect state model with the exponential distribution in the band tail state, which has been proposed by other research groups. In this paper, the three working modes of double-gate Zn O TFT are compared, and it is determined that the top-bottom gate short-circuit mode is used for the following research, and then the effects of deep energy level and band-tail defect state on the performance of the device are studied. The effect of the location and thickness of the source leakage electrode on the performance of the device is also discussed. The results show that the defect state with tail state mainly affects the open state characteristics of the device, while the deep level has a greater effect on the opening voltage, and the characteristics of the device with the top contact of the source and leakage pole are better than that of the bottom contact. On the basis of the above, it is proposed that the double gate composite dielectric Zn O TFT, gate insulation layer uses Si O2-Hf O2-Si O 2 sandwich structure. By comparing the performance of double gate single dielectric Zn O TFT and double gate composite dielectric Zn O TFT, it is found that the double gate composite dielectric Zn O TFT performance is better than that of double gate composite dielectric Zn O TFT. The improvement mechanism of the device performance was studied from the aspects of carrier distribution, channel energy band distribution, grain boundary barrier height (Vb) change, and the distribution of electric field and potential in the channel. The influence factors of thin film transistor with high k material are studied. The higher the dielectric constant of high k material, the better the performance of the device, the smaller the film thickness of high k material is, the greater the proportion in the insulating layer is, and the better the performance of the device is. With different high-k materials, the gate has different control effect on the channel. Finally, the relationship between the threshold voltage and the variation of the grain boundary barrier height (Vb) is studied, and the conclusion that the VGS corresponding to the maximum value of Vb is basically consistent with the threshold voltage extracted by simulation is obtained.
【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN321.5
本文編號(hào)：2253565
[Abstract]:With the development of information age, the development of active drive flat panel display technology is more and more extensive in the field of display technology. Thin film transistor (Thin-film Transistor,TFT), as an important component of active matrix liquid crystal display (AMLCD), has been paid more and more attention. Zinc oxide thin film transistor (Zn O TFT) has a wide application prospect in flexible and transparent electronics because of its high mobility, suitable for low temperature production and good transmittance. Zno TFT can not only solve the opacity of silicon based TFT, but also have poor Guang Min property. The complex preparation process effectively avoids the phenomenon of low carrier mobility and high power consumption in organic thin film transistors. Therefore, more and more institutions began to study the course of Zn O TFT. With the rapid development of integrated circuit, it is absolutely impossible to design and optimize the process level condition by the way of process flow sheet. Therefore, it is imperative to realize the digital simulation and simulation of integrated circuit processing process. However, so far, the research on ZnO thin film transistors is mainly focused on the fabrication process, but the device modeling is very limited. In this paper, the modeling and device simulation of double-gate Zn O TFT are mainly carried out. The model is based on the deep level defect state in the center Gao Si distribution of the forbidden band and the defect state model with the exponential distribution in the band tail state, which has been proposed by other research groups. In this paper, the three working modes of double-gate Zn O TFT are compared, and it is determined that the top-bottom gate short-circuit mode is used for the following research, and then the effects of deep energy level and band-tail defect state on the performance of the device are studied. The effect of the location and thickness of the source leakage electrode on the performance of the device is also discussed. The results show that the defect state with tail state mainly affects the open state characteristics of the device, while the deep level has a greater effect on the opening voltage, and the characteristics of the device with the top contact of the source and leakage pole are better than that of the bottom contact. On the basis of the above, it is proposed that the double gate composite dielectric Zn O TFT, gate insulation layer uses Si O2-Hf O2-Si O 2 sandwich structure. By comparing the performance of double gate single dielectric Zn O TFT and double gate composite dielectric Zn O TFT, it is found that the double gate composite dielectric Zn O TFT performance is better than that of double gate composite dielectric Zn O TFT. The improvement mechanism of the device performance was studied from the aspects of carrier distribution, channel energy band distribution, grain boundary barrier height (Vb) change, and the distribution of electric field and potential in the channel. The influence factors of thin film transistor with high k material are studied. The higher the dielectric constant of high k material, the better the performance of the device, the smaller the film thickness of high k material is, the greater the proportion in the insulating layer is, and the better the performance of the device is. With different high-k materials, the gate has different control effect on the channel. Finally, the relationship between the threshold voltage and the variation of the grain boundary barrier height (Vb) is studied, and the conclusion that the VGS corresponding to the maximum value of Vb is basically consistent with the threshold voltage extracted by simulation is obtained.
【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN321.5
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