RF LDMOS功率晶體管的特性分析與模型研究
發(fā)布時(shí)間：2018-09-12 16:38
【摘要】：RF LDMOS(Radio Frequency Lateral Double Diffused Metal Oxide Silicon)以其增益高、線性好、輸出功率大、穩(wěn)定性好、價(jià)格低廉等優(yōu)點(diǎn)成為通信基站,射頻雷達(dá)中的首選器件。然而國(guó)內(nèi)對(duì)于RF LDMOS功率晶體管的研究尚不成熟,本文基于國(guó)內(nèi)研究現(xiàn)狀開(kāi)展了一款S波段工作的RF LDMOS器件的設(shè)計(jì)與研制。本文所設(shè)計(jì)的RF LDMOS晶體管源極采用Trench Sinker結(jié)構(gòu)將LDMOS源極引到P型重?fù)诫s襯底,雙區(qū)LDD(Lightly Doped Drain)漂移區(qū)結(jié)構(gòu)優(yōu)化器件擊穿電壓和導(dǎo)通電阻,源極金屬場(chǎng)板調(diào)制柵邊緣電場(chǎng)、降低柵漏電容�；诖薘F LDMOS器件的基本結(jié)構(gòu)使用TCAD仿真工具Silvaco進(jìn)行了工藝仿真。折衷優(yōu)化了RF LDMOS的比導(dǎo)通電阻、柵氧可靠性和擊穿電壓,確定了器件的Pbody區(qū)注入劑量、移區(qū)長(zhǎng)度、漂移區(qū)摻雜分布、金屬場(chǎng)板長(zhǎng)度、場(chǎng)板下方氧化層厚度等參數(shù)。根據(jù)仿真優(yōu)化設(shè)計(jì)的的RF LDMOS器件結(jié)構(gòu)進(jìn)行了流片實(shí)驗(yàn),器件擊穿電壓為76V,正向飽和電流密度225mA/mm。通過(guò)柵極的L型預(yù)匹配網(wǎng)絡(luò)與漏極的T型預(yù)匹配網(wǎng)絡(luò),提升了器件的輸入輸出阻抗。封裝后RF LDMOS的測(cè)試結(jié)果表明:在工作電壓30V,2.7-3.1GHz工作頻率下,漏極效率大于40%,輸出功率大于100W,功率增益大于10dB,達(dá)到預(yù)期設(shè)計(jì)目標(biāo)。最后,針對(duì)所研制的RF LDMOS晶體管開(kāi)展了電路模型研究。一方面基于RF LDMOS小信號(hào)電路模型,使用COLD-FET法提取了器件的寄生參數(shù),通過(guò)寄生參數(shù)剝離技術(shù)得到了LDMOS器件的本征元件參數(shù),經(jīng)過(guò)ADS仿真優(yōu)化得到了更為精確的LDMOS小信號(hào)電路模型參數(shù)。另一方面,在小信號(hào)模型的基礎(chǔ)上建立了RF LDMOS的大信號(hào)模型。其中LDMOS的非線性電流模型的建立以摩托羅拉的MET模型為基礎(chǔ)并進(jìn)行了適當(dāng)改進(jìn),非線性電容模型的建立借鑒了傳統(tǒng)的經(jīng)驗(yàn)公式,模型的擬合結(jié)果顯示所建立的大信號(hào)模型可以較準(zhǔn)確的描述LDMOS器件的電流和電容。
[Abstract]:Because of its high gain, good linearity, high output power, good stability and low price, RF LDMOS (Radio Frequency Lateral Double Diffused Metal Oxide Silicon) has become the preferred device in radio frequency radar and communication base station. However, the research of RF LDMOS power transistors in China is not yet mature. In this paper, a S-band working RF LDMOS device is designed and developed based on the domestic research status. The RF LDMOS transistor source pole designed in this paper uses Trench Sinker structure to lead the LDMOS source pole to the P-type heavily doped substrate. The double-zone LDD (Lightly Doped Drain) drift region structure optimizes the breakdown voltage and on-resistance of the device, and the source electrode metal field plate modulates the edge electric field of the gate. Reduce gate leakage capacitance. The basic structure of the RF LDMOS device is simulated by TCAD simulation tool Silvaco. The specific on-resistance, gate oxygen reliability and breakdown voltage of RF LDMOS are optimized, and the parameters of Pbody region implantation dose, shift region length, drift region doping distribution, metal field plate length and oxide layer thickness under the field plate are determined. According to the optimized design of RF LDMOS device structure, the chip experiment is carried out. The breakdown voltage of the device is 76V, and the forward saturation current density is 225 Ma / mmm. The input and output impedance of the device is enhanced by the L-type prematching network of the gate and the T-type prematching network of the drain. The test results of the packaged RF LDMOS show that the drain efficiency is greater than 40, the output power is more than 100W, and the power gain is more than 10dB at the operating frequency of 30VL 2.7-3.1GHz, which achieves the expected design goal. Finally, the circuit model of the developed RF LDMOS transistor is studied. On the one hand, based on the RF LDMOS small-signal circuit model, the parasitic parameters of LDMOS devices are extracted by COLD-FET method, and the intrinsic component parameters of LDMOS devices are obtained by the parasitic parameter stripping technique. More accurate parameters of LDMOS small-signal circuit model are obtained by ADS simulation optimization. On the other hand, the large signal model of RF LDMOS is established on the basis of small signal model. The establishment of nonlinear current model of LDMOS is based on Motorola's MET model and is improved appropriately. The establishment of nonlinear capacitance model draws lessons from the traditional empirical formula. The fitting results show that the large signal model can accurately describe the current and capacitance of LDMOS devices.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
[Abstract]:Because of its high gain, good linearity, high output power, good stability and low price, RF LDMOS (Radio Frequency Lateral Double Diffused Metal Oxide Silicon) has become the preferred device in radio frequency radar and communication base station. However, the research of RF LDMOS power transistors in China is not yet mature. In this paper, a S-band working RF LDMOS device is designed and developed based on the domestic research status. The RF LDMOS transistor source pole designed in this paper uses Trench Sinker structure to lead the LDMOS source pole to the P-type heavily doped substrate. The double-zone LDD (Lightly Doped Drain) drift region structure optimizes the breakdown voltage and on-resistance of the device, and the source electrode metal field plate modulates the edge electric field of the gate. Reduce gate leakage capacitance. The basic structure of the RF LDMOS device is simulated by TCAD simulation tool Silvaco. The specific on-resistance, gate oxygen reliability and breakdown voltage of RF LDMOS are optimized, and the parameters of Pbody region implantation dose, shift region length, drift region doping distribution, metal field plate length and oxide layer thickness under the field plate are determined. According to the optimized design of RF LDMOS device structure, the chip experiment is carried out. The breakdown voltage of the device is 76V, and the forward saturation current density is 225 Ma / mmm. The input and output impedance of the device is enhanced by the L-type prematching network of the gate and the T-type prematching network of the drain. The test results of the packaged RF LDMOS show that the drain efficiency is greater than 40, the output power is more than 100W, and the power gain is more than 10dB at the operating frequency of 30VL 2.7-3.1GHz, which achieves the expected design goal. Finally, the circuit model of the developed RF LDMOS transistor is studied. On the one hand, based on the RF LDMOS small-signal circuit model, the parasitic parameters of LDMOS devices are extracted by COLD-FET method, and the intrinsic component parameters of LDMOS devices are obtained by the parasitic parameter stripping technique. More accurate parameters of LDMOS small-signal circuit model are obtained by ADS simulation optimization. On the other hand, the large signal model of RF LDMOS is established on the basis of small signal model. The establishment of nonlinear current model of LDMOS is based on Motorola's MET model and is improved appropriately. The establishment of nonlinear capacitance model draws lessons from the traditional empirical formula. The fitting results show that the large signal model can accurately describe the current and capacitance of LDMOS devices.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
【相似文獻(xiàn)】
相關(guān)期刊論文 前10條
1 ;今年世界功率晶體管創(chuàng)新高[J];電子產(chǎn)品世界;2011年09期
2 ;功率晶體管突破3GC難關(guān)[J];壓電與聲光;1970年03期
3 K.M.古^，
本文編號(hào)：2239600
本文鏈接：http://lk138.cn/kejilunwen/dianzigongchenglunwen/2239600.html
最近更新
教材專著
