發(fā)布時(shí)間：2018-05-05 00:04

  本文選題：陣列雷達(dá) + 信號(hào)處理　； 參考：《南京理工大學(xué)》2015年碩士論文

【摘要】：圓陣?yán)走_(dá)作為相控陣?yán)走_(dá)的一種形式,具有全方位多波束、大數(shù)據(jù)量的特點(diǎn),對信號(hào)處理提出了很高的要求。而FPGA的高速發(fā)展使得其在處理規(guī)模和速度方面都具有極大的優(yōu)勢,從而在雷達(dá)信號(hào)處理中占據(jù)了重要地位。本文結(jié)合雷達(dá)系統(tǒng)應(yīng)用背景,探討了一種基于Xilinx最新一代FPGA Virtex-7的雷達(dá)信號(hào)處理方案。本文對于信號(hào)處理系統(tǒng)的研究是按照從理論驗(yàn)證到硬件設(shè)計(jì),再到軟件實(shí)現(xiàn),最后到系統(tǒng)聯(lián)調(diào)的順序進(jìn)行的。首先,選擇線性調(diào)頻寬、窄脈沖復(fù)合信號(hào)以兼顧雷達(dá)對遠(yuǎn)、近距離目標(biāo)的探測能力,給出基于多通道脈沖壓縮和MTD的信號(hào)處理方案,并討論距離旁瓣抑制以及遠(yuǎn)、近距離門拼接的問題,給出系統(tǒng)級的MATLAB仿真,為工程實(shí)現(xiàn)提供理論支持。然后,在進(jìn)行了需求分析的基礎(chǔ)之上,給出信號(hào)處理板的總體設(shè)計(jì)方案,采用Virtex-7作為核心處理器,圍繞它進(jìn)行各模塊電路設(shè)計(jì),包括FPGA配置電路、存儲(chǔ)系統(tǒng)、D/A電路、電源系統(tǒng)以及時(shí)鐘系統(tǒng)的設(shè)計(jì)。隨后,討論了信號(hào)處理在FPGA中的實(shí)現(xiàn),包括FFT、IFFT、復(fù)數(shù)乘法等具體算法以及數(shù)據(jù)無縫緩沖和拼接的實(shí)現(xiàn),針對雷達(dá)多種工作模式給出兼容處理方案,分析了時(shí)間及硬件資源,并利用Modelsim和MATLAB進(jìn)行了聯(lián)合仿真及精度分析。最后,對硬件平臺(tái)進(jìn)行系統(tǒng)調(diào)試,給出了時(shí)鐘系統(tǒng)、存儲(chǔ)系統(tǒng)以及D/A電路的調(diào)試結(jié)果,通過在線調(diào)試工具ChipScope對FPGA實(shí)際信號(hào)處理結(jié)果進(jìn)行分析及驗(yàn)證。本文所研究的基于FPGA的信號(hào)處理系統(tǒng)在時(shí)間資源、硬件資源以及實(shí)時(shí)性、正確性上都滿足了陣列雷達(dá)信號(hào)處理的要求,為以后的進(jìn)一步研究提供了技術(shù)積累。
[Abstract]:As a kind of phased array radar, circular array radar has the characteristics of omnidirectional multi-beam and large amount of data. With the rapid development of FPGA, it has a great advantage in processing scale and speed, so it plays an important role in radar signal processing. Based on the background of radar system application, a radar signal processing scheme based on the latest generation FPGA Virtex-7 of Xilinx is discussed in this paper. In this paper, the research of signal processing system is carried out according to the sequence from theoretical verification to hardware design, software implementation, and finally to the system combination. Firstly, the signal processing scheme based on multi-channel pulse compression and MTD is presented, and the range sidelobe suppression and the distance sidelobe suppression are discussed. The system level MATLAB simulation is presented to provide theoretical support for engineering implementation. Then, based on the requirement analysis, the overall design scheme of the signal processing board is given. The Virtex-7 is used as the core processor, and every module circuit is designed around it, including the FPGA configuration circuit, the storage system D / A circuit. Design of power system and clock system. Then, the realization of signal processing in FPGA is discussed, including the implementation of FFTFT-IFFTFT, complex multiplication and seamless data buffering and splicing. The compatible processing scheme is given for various working modes of radar, and the time and hardware resources are analyzed. The joint simulation and precision analysis are carried out by Modelsim and MATLAB. Finally, the hardware platform is debugged, and the debugging results of clock system, storage system and D / A circuit are given. The actual signal processing results of FPGA are analyzed and verified by on-line debugging tool ChipScope. In this paper, the signal processing system based on FPGA meets the requirements of array radar signal processing in terms of time resources, hardware resources and real-time, and provides a technical accumulation for further research.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN957.51

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本文編號(hào)：1845271