發(fā)布時(shí)間：2018-07-16 15:09

【摘要】：總線遍布于整個(gè)計(jì)算機(jī)系統(tǒng)之中，使計(jì)算機(jī)系統(tǒng)的各個(gè)部分成為一個(gè)整體。它攜帶著有效信息，傳遞在計(jì)算機(jī)系統(tǒng)的不同部分之間，將各個(gè)部分的功能進(jìn)行綜合來完成系統(tǒng)的功能。計(jì)算機(jī)速度不斷提高的今天，顯卡、內(nèi)存、CPU等組成部分性能飛速發(fā)展，，總線日益成為計(jì)算機(jī)系統(tǒng)的性能瓶頸。 本課題來源于科研項(xiàng)目Fiber Channel協(xié)議芯片研制。由于目前行業(yè)內(nèi)廣泛使用的PCI總線所能提供的最大帶寬為133MB/s，不能滿足該芯片的要求，因此本次芯片設(shè)計(jì)中采用第三代通用IO總線標(biāo)準(zhǔn)PCI Express協(xié)議�；�于PCI Express協(xié)議的PCIe總線具有很多優(yōu)良特性，如高帶寬，低延遲，抗干擾性強(qiáng)，高擴(kuò)展性，高可靠性。PCIe總線采用點(diǎn)到點(diǎn)連接，保證了消息的實(shí)時(shí)性，基于交換器的設(shè)計(jì)，增加了下掛能力，使得PCIe的性能提升到一個(gè)新的層次。我們所要做的就是將PCIExpress協(xié)議的理論優(yōu)勢(shì)轉(zhuǎn)化為實(shí)際應(yīng)用中的優(yōu)勢(shì)。 本次論文分為理論，實(shí)現(xiàn)及驗(yàn)證三部分。理論部分根據(jù)PCI Express協(xié)議，介紹了PCI Express的基本概念，重點(diǎn)介紹了事務(wù)層和數(shù)據(jù)鏈路層的基本功能以及這兩層的數(shù)據(jù)包的構(gòu)成方式和功能。實(shí)現(xiàn)部分基本按照PCI Express協(xié)議，以高性能，低延遲為目標(biāo)，按照IC設(shè)計(jì)的流程，基本實(shí)現(xiàn)了PCI Express事務(wù)層和數(shù)據(jù)鏈路層的功能。事務(wù)層和數(shù)據(jù)鏈路層的設(shè)計(jì)各分為兩大模塊發(fā)送模塊和接收模塊，另外附加一些額外功能模塊，例如流量控制等。驗(yàn)證的部分重點(diǎn)在于驗(yàn)證平臺(tái)的搭建，本文中搭建的驗(yàn)證平臺(tái)包含自動(dòng)檢測(cè)模塊，對(duì)于驗(yàn)證結(jié)果實(shí)現(xiàn)自動(dòng)比對(duì)，大幅度減輕了驗(yàn)證工作的效率。同時(shí)由于PCI Express設(shè)備即可作為根復(fù)合體，又可作為端點(diǎn)設(shè)備來工作，因此在本次驗(yàn)證平臺(tái)的搭建中對(duì)協(xié)議代碼模塊進(jìn)行的復(fù)用，降低了驗(yàn)證平臺(tái)搭建的難度。最后對(duì)整個(gè)PCIe模塊進(jìn)行了系統(tǒng)的驗(yàn)證，并得到了較好的結(jié)果。
[Abstract]:The bus is spread throughout the computer system, making all parts of the computer system a whole. It carries the effective information and transmits between different parts of the computer system. The functions of each part are integrated to complete the function of the system. With the increasing of computer speed, the performance of graphics card and memory CPU is developing rapidly, and bus is becoming the bottleneck of computer system performance. This topic comes from the research project fiber channel protocol chip development. The PCI bus, which is widely used in the industry, can provide the maximum bandwidth of 133MB / s, which can not meet the requirements of the chip, so the third generation PCI Express protocol is adopted in the design of the chip. PCIe bus based on PCI Express protocol has many excellent characteristics, such as high bandwidth, low delay, strong anti-interference, high expansibility, high reliability. Increased the ability to hang down, so that the performance of PCIe to a new level. What we have to do is to convert the theoretical advantage of PCI Express protocol into the advantage of practical application. This paper is divided into three parts: theory, realization and verification. In the theoretical part, the basic concept of PCI Express is introduced according to PCI Express protocol, and the basic functions of transaction layer and data link layer are emphatically introduced, as well as the composition and function of these two layers of data packets. In the realization part, PCI Express transaction layer and data link layer are basically realized according to PCI Express protocol, high performance, low delay as the target, according to the flow chart designed by IC. The design of transaction layer and data link layer is divided into two modules: sending module and receiving module, and some additional function modules, such as flow control, etc. Part of the emphasis of verification is the construction of verification platform. The verification platform built in this paper contains automatic detection module. The verification results are compared automatically and the efficiency of verification work is greatly reduced. At the same time, the PCI Express device can be used as the root complex and the endpoint device to work, so the reuse of the protocol code module in this verification platform reduces the difficulty of building the verification platform. Finally, the whole PCIe module is systematically verified, and good results are obtained.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP336

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