車用微控制器運算和譯碼部件的設計與驗證
發(fā)布時間：2018-07-15 07:39
【摘要】：汽車電子是現(xiàn)代汽車中一個發(fā)展迅猛的領域，，ECU（Electrical Control Unit）在其中扮演著非常重要的角色。為了實現(xiàn)汽車電子的智能化和網絡化，汽車中需要集成更多的ECU。但是ECU的核心部件微控制器卻被國外廠商長期壟斷，這對大力發(fā)展國內的汽車工業(yè)來說是一個障礙。所以進行自主知識產權車用微控制器的設計和研發(fā)具有重要意義。 在分析了車用微控制器特點的基礎上，我們確定了研究目標：實現(xiàn)一款兼容飛思卡爾CPU12指令集的16位車用微控制器。整個微控制器核心采用了單時鐘同步設計和微程序控制的總體設計方案，提高了系統(tǒng)的穩(wěn)定性和靈活性。本文主要負責微控制器運算和譯碼部件的設計與驗證。首先，本文提出了具有統(tǒng)一數(shù)據通路和快速運算模塊的運算部件。提出的數(shù)據通路使用一個運算模塊就可以滿足一類指令的8位和16位有符號和無符號運算，避免了運算模塊的重復，從而減少了部件面積。性能評估的結果表明設計的運算部件完全可以滿足微控制器的要求。其次，在對所有指令結構和特征深入分析的基礎上，提出了一種兼容CPU12指令集的譯碼方案，結合提出的高效預取機制，可以快速讀入指令字節(jié)，從而加快了譯碼信息的產生，提高了微控制器的效率。 面對復雜設計帶來的驗證挑戰(zhàn)，本文對驗證語言和驗證方法學進行了相關研究，并搭建了基于UVM（Universal Verification Methodology）的可重用驗證平臺，進行了基于覆蓋率和斷言的模塊級驗證，提高了設計和驗證的質量。本文設計了基于隨機約束的事務級指令發(fā)生器，此發(fā)生器可有效地產生各種符合指令集格式的指令，大大減少了人工定向激勵的編寫。結合針對接口信號和內部狀態(tài)設計的并行斷言，加快了模塊級的調試過程和驗證收斂，實現(xiàn)了部件的較全面驗證。最后進行了系統(tǒng)級的調試和FPGA原型測試。
[Abstract]:Electrical Control Unit (ECU) plays a very important role in modern automobile. In order to realize the intelligence and network of automobile electronics, more ECUs need to be integrated in automobile. However, the core component of ECU microcontroller has been monopolized by foreign manufacturers for a long time, which is an obstacle to the development of domestic automobile industry. Therefore, it is of great significance to design and develop independent intellectual property vehicle microcontrollers. On the basis of analyzing the characteristics of vehicle microcontroller, we have determined the research goal: to realize a 16-bit vehicle microcontroller compatible with Freescale CPU12 instruction set. The whole microcontroller core adopts the single clock synchronization design and the overall design scheme of microprogram control, which improves the stability and flexibility of the system. This paper is mainly responsible for the design and verification of microcontroller operation and decoding parts. First of all, this paper proposes a unified data path and fast operation module. Using one operation module, the proposed data path can satisfy the 8-bit and 16-bit signed and unsigned operations of a class of instructions, thus avoiding the repetition of the operation modules and thus reducing the area of the parts. The performance evaluation results show that the designed computing unit can fully meet the requirements of the microcontroller. Secondly, a decoding scheme compatible with CPU12 instruction set is proposed on the basis of in-depth analysis of all instruction structures and features. Combined with the proposed efficient prefetching mechanism, it can quickly read instruction bytes, thus speeding up the generation of decoding information. The efficiency of microcontroller is improved. In the face of the verification challenges brought by complex design, this paper studies the verification language and verification methodology, builds a reusable verification platform based on UVM (Universal Verification Methodology), and implements modular verification based on coverage and assertion. The quality of design and verification is improved. In this paper, a transaction level instruction generator based on random constraints is designed. This generator can effectively generate instructions in accordance with instruction set format and greatly reduce the writing of manual directional excitation. Combined with the parallel assertions designed for interface signals and internal states, the debugging process and verification convergence at the module level are accelerated, and the complete verification of the components is realized. Finally, system level debugging and FPGA prototype test are carried out.
【學位授予單位】：湖南大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332
本文編號：2123352
[Abstract]:Electrical Control Unit (ECU) plays a very important role in modern automobile. In order to realize the intelligence and network of automobile electronics, more ECUs need to be integrated in automobile. However, the core component of ECU microcontroller has been monopolized by foreign manufacturers for a long time, which is an obstacle to the development of domestic automobile industry. Therefore, it is of great significance to design and develop independent intellectual property vehicle microcontrollers. On the basis of analyzing the characteristics of vehicle microcontroller, we have determined the research goal: to realize a 16-bit vehicle microcontroller compatible with Freescale CPU12 instruction set. The whole microcontroller core adopts the single clock synchronization design and the overall design scheme of microprogram control, which improves the stability and flexibility of the system. This paper is mainly responsible for the design and verification of microcontroller operation and decoding parts. First of all, this paper proposes a unified data path and fast operation module. Using one operation module, the proposed data path can satisfy the 8-bit and 16-bit signed and unsigned operations of a class of instructions, thus avoiding the repetition of the operation modules and thus reducing the area of the parts. The performance evaluation results show that the designed computing unit can fully meet the requirements of the microcontroller. Secondly, a decoding scheme compatible with CPU12 instruction set is proposed on the basis of in-depth analysis of all instruction structures and features. Combined with the proposed efficient prefetching mechanism, it can quickly read instruction bytes, thus speeding up the generation of decoding information. The efficiency of microcontroller is improved. In the face of the verification challenges brought by complex design, this paper studies the verification language and verification methodology, builds a reusable verification platform based on UVM (Universal Verification Methodology), and implements modular verification based on coverage and assertion. The quality of design and verification is improved. In this paper, a transaction level instruction generator based on random constraints is designed. This generator can effectively generate instructions in accordance with instruction set format and greatly reduce the writing of manual directional excitation. Combined with the parallel assertions designed for interface signals and internal states, the debugging process and verification convergence at the module level are accelerated, and the complete verification of the components is realized. Finally, system level debugging and FPGA prototype test are carried out.
【學位授予單位】：湖南大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332
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