發(fā)布時間：2018-06-13 09:41

  本文選題：PCI + Express鏈路��； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著信息技術(shù)的發(fā)展,數(shù)字信息資源的體積有了較大的膨脹,數(shù)字設(shè)備之間交換數(shù)據(jù)量越來越大。日益增長的數(shù)據(jù)量對高速數(shù)據(jù)傳輸接口的需求變得更加迫切。為滿足這個需求,PCI Express總線技術(shù)應(yīng)運(yùn)而生,并被廣泛應(yīng)用于個人電腦中。隨著嵌入式系統(tǒng)性能的提升,PCI Express總線技術(shù)在嵌入式領(lǐng)域也得到越來越廣泛的應(yīng)用。嵌入式平臺的主要核心基本上是處理器和可編程邏輯器件(FPGA)兩部分,而且越來越多的處理器和FPGA支持高速PCI Express總線接口�；�于此,本文研究了PCI Express技術(shù)在基于FPGA和處理器平臺中的高速數(shù)據(jù)傳輸應(yīng)用,設(shè)計并實(shí)現(xiàn)了一種FPGA與PowerPC處理器通信方案,并且在該方案的基礎(chǔ)上,進(jìn)一步對PCI Express技術(shù)在多個PowerPC處理器通信中的應(yīng)用進(jìn)行了探索和實(shí)踐,最終實(shí)現(xiàn)了多個嵌入式PowerPC處理器的PCIe通信方案。在FPGA與處理器的PCIe通信系統(tǒng)中,由嵌入式PowerPC處理器作為根復(fù)合體(RC)設(shè)備,FPGA作為EP(端點(diǎn))設(shè)備,二者直接建立PCIe鏈路進(jìn)行通信;而在多個嵌入式PowerPC處理器的PCIe通信系統(tǒng)中,由一顆PowerPC處理器作為RC設(shè)備,其它PowerPC處理器作為EP設(shè)備,并通過交換芯片對PCIe鏈路進(jìn)行擴(kuò)展,建立起一對多的PCIe鏈路。所介紹的兩種嵌入式平臺的軟件設(shè)計均基于嵌入式Linux系統(tǒng),Linux應(yīng)用程序通過PCIe設(shè)備驅(qū)動程序?qū)崿F(xiàn)了對PCIe鏈路的初始化和控制。本文在兩種嵌入式平臺上所完成的工作有:1.在FPGA與嵌入式PowerPC處理器的PCIe通信系統(tǒng)中,基于Xilinx公司的Virtex6系列FPGA的片內(nèi)PCIe核實(shí)現(xiàn)了PCIe EP設(shè)備,與作為RC設(shè)備的MPC8377處理器建立PCIe鏈路。運(yùn)行在MPC8377上的嵌入式Linux應(yīng)用程序配合EP驅(qū)動程序訪問FPGA,實(shí)現(xiàn)FPGA和PowerPC處理器的通信。2.在多個嵌入式Power PC處理器的PCIe通信系統(tǒng)中,實(shí)現(xiàn)了多顆MPC8377的PCIe通信。其中一顆處理器在switch上游作為RC設(shè)備,而其它處理器在switch下游作為EP設(shè)備。運(yùn)行在RC端的嵌入式Linux應(yīng)用程序配合EP驅(qū)動程序,實(shí)現(xiàn)了與EP處理器的通信。論文分別給出了兩種嵌入式平臺運(yùn)行測試的結(jié)果,證明其完全滿足設(shè)計要求。
[Abstract]:With the development of information technology, the volume of digital information resources has expanded greatly. The demand of high-speed data transmission interface becomes more and more urgent due to the increasing amount of data. In order to meet this requirement, PCI Express bus technology emerged as the times require, and has been widely used in personal computers. With the improvement of embedded system performance, PCI Express bus technology has been more and more widely used in embedded field. The main core of embedded platform is basically processor and programmable logic device (FPGA), and more processors and FPGA support high-speed PCI Express bus interface. Based on this, this paper studies the application of PCI Express technology in high speed data transmission based on FPGA and processor platform, and designs and implements a communication scheme between FPGA and PowerPC processor. Furthermore, the application of PCI Express technology in multiple PowerPC processors is explored and put into practice. Finally, the PCIe communication scheme of multiple embedded PowerPC processors is implemented. In the PCIe communication system between FPGA and processor, the embedded PowerPC processor is used as the root complex device and FPGA is used as the EPIe device, and the PCIe link is directly established for communication between the two devices, while in the PCIe communication system of multiple embedded PowerPC processors, Using one PowerPC processor as RC device and other PowerPC processors as EP devices, a one-to-many PCIe link is established by extending the PCIe link through switching chips. The software design of the two embedded platforms is based on the embedded Linux system and Linux application program, which realizes the initialization and control of the PCIe link through the PCIe device driver. The work of this paper on two embedded platforms is: 1. 1. In the PCIe communication system between FPGA and embedded PowerPC processor, the PCIe core based on Xilinx's Virtex6 series FPGA implements the PCIe EP device, and establishes the PCIe link with the MPC8377 processor as the RC device. The embedded Linux application running on MPC8377 accesses FPGA with EP driver, and realizes the communication between FPGA and PowerPC processor. In the PCIe communication system of multiple embedded Power PC processors, the PCIe communication of MPC8377 is realized. One processor acts as a RC device upstream of the switch, while the other processor acts as an EP device downstream of the switch. The embedded Linux application running in RC terminal cooperates with EP driver to realize communication with EP processor. The test results of two kinds of embedded platform are given in this paper, and it is proved that they can meet the design requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP336

【參考文獻(xiàn)】

相關(guān)期刊論文 前3條

1 賈真;林清;;PCI總線應(yīng)用設(shè)計與研究[J];現(xiàn)代電子技術(shù);2008年10期

2 郭紹日;張振宇;;PCI Express總線技術(shù)剖析[J];電子測試;2004年11期

3 陳世平;高分辨率衛(wèi)星遙感數(shù)據(jù)傳輸技術(shù)發(fā)展的若干問題[J];空間電子技術(shù);2003年03期

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本文編號：2013581