發(fā)布時(shí)間：2019-05-16 16:53

【摘要】：為某項(xiàng)目設(shè)計(jì)一款頻率在2 GHz~3 GHz寬帶跳頻源,頻率間隔為1 MHz,跳頻點(diǎn)數(shù)為1 001點(diǎn)。該跳頻源要求相位噪聲小于-100 dBc@1 kHz,雜散優(yōu)于60 dB。分析指標(biāo)和軟件仿真計(jì)算,采用HITTITE公司的HMC830鎖相芯片來(lái)實(shí)現(xiàn)該設(shè)計(jì)方案。采用HITTITE公司的PLL仿真設(shè)計(jì)軟件對(duì)環(huán)路濾波器進(jìn)行優(yōu)化設(shè)計(jì)后應(yīng)用到實(shí)際電路中,使得該芯片在-55℃到+85℃均可穩(wěn)定工作。通過(guò)外接串口通信控制模塊,實(shí)現(xiàn)頻率的跳變。最終該設(shè)計(jì)的實(shí)物測(cè)試相位噪聲、雜散指標(biāo)均優(yōu)于目標(biāo)值。測(cè)試得到該頻率源相位噪聲可達(dá)到-100 dBc/Hz@1 kHz,雜散指標(biāo)能夠達(dá)到-70 dB,具有工程應(yīng)用價(jià)值
[Abstract]:For a project, a wideband frequency hopping source with a frequency of 2 GHz to 3 GHz is designed, with a frequency interval of 1 MHz and a frequency hopping number of 1 001. The frequency-hopping source requires that the phase noise be less than -100 dBc@1 kHz and the spur is better than 60 dB. The design scheme is realized by using the HMC830 phase-lock chip of the HITTITE company based on the analysis index and the software simulation calculation. The design of the loop filter by the PLL simulation design software of HITTITE is applied to the real circuit, so that the chip can work stably at -55 鈩，

本文編號(hào)：2478422