MOS器件界面態(tài)特性研究及其可靠性分析
發(fā)布時間：2019-05-11 10:43
【摘要】：自集成電路工藝發(fā)展到深亞微米技術以來,器件的可靠性問題已成為阻礙集成電路工藝水平沿著Moore定律繼續(xù)延伸的主要困難之一。研究表明,在深亞微米MOS工藝中,器件的可靠性問題愈加凸顯,除了尺寸減小導致電場增強之外,工藝的改進也會帶來新的可靠性問題。由此,本文針對65nm工藝下MOS器件的退化特性等可靠性問題展開研究,并深入分析了電荷泵技術在1um MOS器件界面態(tài)密度測量中的作用。論文主要研究內容如下:1、電荷泵技術在1um MOS器件界面態(tài)密度測量中的作用。對界面態(tài)密度進行理論分析的結果表明,脈沖頻率、幅值、源漏反偏電壓和器件柵氧化層寬長比等參量,都會影響電荷泵技術測量的可靠性。當測量頻率在10k Hz-6000k Hz范圍內、反偏置電壓在0.3V-1.5V之間、柵脈沖電壓幅值大于3.0V、柵寬度與長度比W/L較大時,電荷泵技術才能準確測量出1um MOS器件的界面態(tài)密度值。2、熱載流子效應對65nm MOS器件可靠性的影響。在加速應力條件下,研究了65nm MOS器件的HCI退化特性,并采用襯底/漏極電流比率模型進行HCI壽命預測。實驗結果發(fā)現(xiàn),熱載流子效應對65nm三柵器件造成嚴重影響,將導致器件出現(xiàn)最大跨導閾值電壓退化和恒定電流閾值電壓退化。3、時間介質擊穿效應對65nm MOS器件可靠性的影響。在加速應力條件下,測量了65nm MOS器件中的TDDB退化特性,并采用新型冪指數(shù)壽命計算模型進行TDDB壽命預測研究。結果表明,時間介質擊穿效應對65nm MOS器件影響較小,然而電壓與溫度提高均可加快器件的TDDB退化。而且,在溫度較低時,器件發(fā)生多次軟擊穿后會再出現(xiàn)硬擊穿現(xiàn)象;在溫度較高時,器件只發(fā)生硬擊穿。綜上所述,本文通過實驗檢測、模型與數(shù)據(jù)分析獲得的結果,可為準確分析1um MOS器件的界面態(tài)密度,以及65nm MOS器件的HCI與TDDB退化機制提供依據(jù)。
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【學位授予單位】：暨南大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
本文編號：2474427
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【學位授予單位】：暨南大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386
【參考文獻】
相關期刊論文 前8條
1 黃勇;恩云飛;章曉文;;NBTI效應的退化表征[J];半導體技術;2007年07期
2 簡維廷;趙永;張榮哲;;柵氧化層經(jīng)時擊穿物理模型應用分析[J];半導體技術;2010年02期
3 楊謨華,于奇,王向展,陳勇,劉玉奎,肖兵,楊沛鋒,方朋,孔學東,譚超元,鐘征宇;MOSFET熱載流子退化/壽命模型參數(shù)提取[J];半導體學報;2000年03期
4 劉紅俠,郝躍;深亞微米pMOS器件的HCI和NBTI耦合效應與物理機制[J];半導體學報;2005年09期
5 翁壽松;摩爾定律與半導體設備[J];電子工業(yè)專用設備;2002年04期
6 胡恒升,張敏,林立謹;TDDB擊穿特性評估薄介質層質量[J];電子學報;2000年05期
7 王茂菊,李斌,章曉文,陳平,韓靜;薄柵氧化層斜坡電壓TDDB壽命評價[J];微電子學;2005年04期
8 拓耀飛;李少宏;;論結構可靠性的發(fā)展[J];榆林學院學報;2006年04期
相關碩士學位論文 前1條
1 邢德智;超深亞微米NMOSFET中的熱載流子效應[D];西安電子科技大學;2007年
，本文編號：2474427
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