MOS器件界面態(tài)特性研究及其可靠性分析
發(fā)布時(shí)間：2019-05-11 10:43
【摘要】：自集成電路工藝發(fā)展到深亞微米技術(shù)以來(lái),器件的可靠性問(wèn)題已成為阻礙集成電路工藝水平沿著Moore定律繼續(xù)延伸的主要困難之一。研究表明,在深亞微米MOS工藝中,器件的可靠性問(wèn)題愈加凸顯,除了尺寸減小導(dǎo)致電場(chǎng)增強(qiáng)之外,工藝的改進(jìn)也會(huì)帶來(lái)新的可靠性問(wèn)題。由此,本文針對(duì)65nm工藝下MOS器件的退化特性等可靠性問(wèn)題展開(kāi)研究,并深入分析了電荷泵技術(shù)在1um MOS器件界面態(tài)密度測(cè)量中的作用。論文主要研究?jī)?nèi)容如下:1、電荷泵技術(shù)在1um MOS器件界面態(tài)密度測(cè)量中的作用。對(duì)界面態(tài)密度進(jìn)行理論分析的結(jié)果表明,脈沖頻率、幅值、源漏反偏電壓和器件柵氧化層寬長(zhǎng)比等參量,都會(huì)影響電荷泵技術(shù)測(cè)量的可靠性。當(dāng)測(cè)量頻率在10k Hz-6000k Hz范圍內(nèi)、反偏置電壓在0.3V-1.5V之間、柵脈沖電壓幅值大于3.0V、柵寬度與長(zhǎng)度比W/L較大時(shí),電荷泵技術(shù)才能準(zhǔn)確測(cè)量出1um MOS器件的界面態(tài)密度值。2、熱載流子效應(yīng)對(duì)65nm MOS器件可靠性的影響。在加速應(yīng)力條件下,研究了65nm MOS器件的HCI退化特性,并采用襯底/漏極電流比率模型進(jìn)行HCI壽命預(yù)測(cè)。實(shí)驗(yàn)結(jié)果發(fā)現(xiàn),熱載流子效應(yīng)對(duì)65nm三柵器件造成嚴(yán)重影響,將導(dǎo)致器件出現(xiàn)最大跨導(dǎo)閾值電壓退化和恒定電流閾值電壓退化。3、時(shí)間介質(zhì)擊穿效應(yīng)對(duì)65nm MOS器件可靠性的影響。在加速應(yīng)力條件下,測(cè)量了65nm MOS器件中的TDDB退化特性,并采用新型冪指數(shù)壽命計(jì)算模型進(jìn)行TDDB壽命預(yù)測(cè)研究。結(jié)果表明,時(shí)間介質(zhì)擊穿效應(yīng)對(duì)65nm MOS器件影響較小,然而電壓與溫度提高均可加快器件的TDDB退化。而且,在溫度較低時(shí),器件發(fā)生多次軟擊穿后會(huì)再出現(xiàn)硬擊穿現(xiàn)象;在溫度較高時(shí),器件只發(fā)生硬擊穿。綜上所述,本文通過(guò)實(shí)驗(yàn)檢測(cè)、模型與數(shù)據(jù)分析獲得的結(jié)果,可為準(zhǔn)確分析1um MOS器件的界面態(tài)密度,以及65nm MOS器件的HCI與TDDB退化機(jī)制提供依據(jù)。
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【學(xué)位授予單位】：暨南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
本文編號(hào)：2474427
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【學(xué)位授予單位】：暨南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
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