JPEG2000位平面解碼器VLSI結(jié)構(gòu)設(shè)計
發(fā)布時間：2018-12-13 23:09
【摘要】：隨著計算機技術(shù)、通信技術(shù)、網(wǎng)絡(luò)技術(shù)等技術(shù)快速發(fā)展,數(shù)字圖像被廣泛應(yīng)用于通信、互聯(lián)網(wǎng)、醫(yī)療、電子商務(wù)、遙感衛(wèi)星、軍事、法律等各個領(lǐng)域,導(dǎo)致數(shù)據(jù)量呈指數(shù)級增長。巨大的數(shù)據(jù)量對圖像的處理、存儲和傳輸造成極大壓力,因此圖像壓縮技術(shù)在數(shù)字圖像應(yīng)用中具有重要作用。JPEG2000是一種性能優(yōu)越的圖像壓縮標(biāo)準(zhǔn),具有碼率可控、壓縮倍數(shù)高、適合網(wǎng)絡(luò)傳輸?shù)葍?yōu)點,對自然圖像、合成圖像、衛(wèi)星圖像、醫(yī)學(xué)圖像等各類圖像均具有良好的適用性。目前國內(nèi)已有西安電子科技大學(xué)圖像傳輸與處理研究所研制的高性能JPEG2000編碼芯片“雅芯二號”用于航天領(lǐng)域,但是JPEG2000解碼系統(tǒng)的高速硬件實現(xiàn)仍有待突破。其主要原因是復(fù)雜的解碼算法使JPEG2000難以滿足實時性處理要求,尤其是JPEG2000中的位平面解碼部分的算法復(fù)雜度高、開發(fā)周期長、處理時延大,造成JPEG2000高速硬件解碼系統(tǒng)實現(xiàn)困難。因此,深入研究JPEG2000位平面解碼器硬件實現(xiàn)具有重要意義。在結(jié)合JPEG2000算法標(biāo)準(zhǔn)和FPGA硬件平臺特點的基礎(chǔ)上,本研究的總體目標(biāo)是在Xilinx公司的VC707開發(fā)板上實現(xiàn)JPEG2000解碼系統(tǒng),達到入口速率是100Mbps。本文研究的主要內(nèi)容有以下兩部分:(1)本文設(shè)計了采取列掃描、列跳過方案的3×4的寄存器掃描窗口,并對一列樣本點的上下文采取預(yù)計算的方法,給出了寄存器窗口、上下文生成及更新、四種編碼原語的VLSI結(jié)構(gòu),同時給出了三個通道的狀態(tài)跳轉(zhuǎn)圖,并采用高級綜合HLS(High-level Synthesis)實現(xiàn)位平面解碼部分。對比傳統(tǒng)手寫代碼的開發(fā)方式,HLS具有開發(fā)速度快、方案調(diào)整靈活的優(yōu)點,因而整個位平面解碼器采用HLS實現(xiàn)。(2)本文深入分析JPEG2000解碼系統(tǒng)各部分處理速度,制定了高效存儲調(diào)度方案并完成DDR(Double Data Rate SDRAM)控制器的設(shè)計。本文的工作重點是JPEG2000解碼系統(tǒng)中位平面解碼部分以及DDR存儲調(diào)度部分的研究和實現(xiàn)。采用HLS完成了位平面解碼器設(shè)計,解決了傳統(tǒng)手寫Verilog/VHDL代碼開發(fā)周期長、開發(fā)流程復(fù)雜的問題,并且能通過HLS約束形成各種結(jié)構(gòu)適用于不同速度、不同資源需求的應(yīng)用場景。在VC707開發(fā)板上實現(xiàn)后,位平面解碼器出口速率最高達98.1Mbps,資源占用在3%以內(nèi),比標(biāo)準(zhǔn)算法串行解碼的結(jié)構(gòu)平均吞吐率提高5倍,資源占用減少一半以上。結(jié)合高效的DDR存儲調(diào)度方案,可對入口速率為100Mbps、壓縮倍數(shù)為2倍和4倍的碼流進行處理,能滿足一般的實時處理要求。
[Abstract]:With the rapid development of computer technology, communication technology and network technology, digital image is widely used in many fields, such as communication, Internet, medical treatment, electronic commerce, remote sensing satellite, military, law, etc. This results in an exponential increase in the amount of data. Huge amount of data exerts great pressure on image processing, storage and transmission, so image compression technology plays an important role in digital image application. JPEG2000 is an excellent image compression standard with controllable code rate and high compression multiple. It is suitable for network transmission and has good applicability to natural image, synthetic image, satellite image, medical image and so on. At present, the high performance JPEG2000 coding chip "Yaxin 2" developed by the Institute of Image Transmission and processing of Xi'an University of Electronic Science and Technology has been used in the aerospace field in China, but the high-speed hardware implementation of the JPEG2000 decoding system still needs to be broken through. The main reason is that the complex decoding algorithm makes it difficult for JPEG2000 to meet the requirements of real-time processing. Especially, the bitplane decoding part of JPEG2000 has high complexity, long development cycle and long processing delay, which makes it difficult to implement JPEG2000 high-speed hardware decoding system. Therefore, it is of great significance to study the hardware implementation of JPEG2000 bit plane decoder. Based on the JPEG2000 algorithm standard and the characteristics of FPGA hardware platform, the overall goal of this study is to implement the JPEG2000 decoding system on the VC707 development board of Xilinx Company, and the entry rate is 100 Mbps. The main contents of this paper are as follows: (1) this paper designs a 3 脳 4 register scanning window with column scan and column skipping scheme, and gives a register window by using predictive calculation method for the context of a list of sample points. Context generation and update, VLSI structure of four encoding primitives, and the state jump diagram of three channels are given, and the bit plane decoding part is implemented by advanced synthetic HLS (High-level Synthesis). Compared with the traditional handwritten code development, HLS has the advantages of fast development speed and flexible scheme adjustment, so the whole bit-plane decoder is implemented by HLS. (2) the processing speed of each part of JPEG2000 decoding system is deeply analyzed in this paper. An efficient storage scheduling scheme is developed and the design of DDR (Double Data Rate SDRAM) controller is completed. This paper focuses on the research and implementation of the median bit plane decoding part and the DDR storage scheduling part of the JPEG2000 decoding system. The bit plane decoder is designed by using HLS, which solves the problems of long development cycle and complex development process of traditional handwritten Verilog/VHDL code, and can form various kinds of application scenarios with different speed and different resource requirements through HLS constraints. When implemented on the VC707 development board, the output rate of the bit-plane decoder is up to 98.1Mbpss, and the resource consumption is less than 3%, which is five times higher than the average throughput of the standard serial decoding structure, and the resource consumption is reduced by more than half. Combined with the efficient DDR storage scheduling scheme, the code stream with 100Mbpss entry rate, 2 times compression times and 4 times compression ratio can be processed, which can meet the general real-time processing requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN764
本文編號：2377421
[Abstract]:With the rapid development of computer technology, communication technology and network technology, digital image is widely used in many fields, such as communication, Internet, medical treatment, electronic commerce, remote sensing satellite, military, law, etc. This results in an exponential increase in the amount of data. Huge amount of data exerts great pressure on image processing, storage and transmission, so image compression technology plays an important role in digital image application. JPEG2000 is an excellent image compression standard with controllable code rate and high compression multiple. It is suitable for network transmission and has good applicability to natural image, synthetic image, satellite image, medical image and so on. At present, the high performance JPEG2000 coding chip "Yaxin 2" developed by the Institute of Image Transmission and processing of Xi'an University of Electronic Science and Technology has been used in the aerospace field in China, but the high-speed hardware implementation of the JPEG2000 decoding system still needs to be broken through. The main reason is that the complex decoding algorithm makes it difficult for JPEG2000 to meet the requirements of real-time processing. Especially, the bitplane decoding part of JPEG2000 has high complexity, long development cycle and long processing delay, which makes it difficult to implement JPEG2000 high-speed hardware decoding system. Therefore, it is of great significance to study the hardware implementation of JPEG2000 bit plane decoder. Based on the JPEG2000 algorithm standard and the characteristics of FPGA hardware platform, the overall goal of this study is to implement the JPEG2000 decoding system on the VC707 development board of Xilinx Company, and the entry rate is 100 Mbps. The main contents of this paper are as follows: (1) this paper designs a 3 脳 4 register scanning window with column scan and column skipping scheme, and gives a register window by using predictive calculation method for the context of a list of sample points. Context generation and update, VLSI structure of four encoding primitives, and the state jump diagram of three channels are given, and the bit plane decoding part is implemented by advanced synthetic HLS (High-level Synthesis). Compared with the traditional handwritten code development, HLS has the advantages of fast development speed and flexible scheme adjustment, so the whole bit-plane decoder is implemented by HLS. (2) the processing speed of each part of JPEG2000 decoding system is deeply analyzed in this paper. An efficient storage scheduling scheme is developed and the design of DDR (Double Data Rate SDRAM) controller is completed. This paper focuses on the research and implementation of the median bit plane decoding part and the DDR storage scheduling part of the JPEG2000 decoding system. The bit plane decoder is designed by using HLS, which solves the problems of long development cycle and complex development process of traditional handwritten Verilog/VHDL code, and can form various kinds of application scenarios with different speed and different resource requirements through HLS constraints. When implemented on the VC707 development board, the output rate of the bit-plane decoder is up to 98.1Mbpss, and the resource consumption is less than 3%, which is five times higher than the average throughput of the standard serial decoding structure, and the resource consumption is reduced by more than half. Combined with the efficient DDR storage scheduling scheme, the code stream with 100Mbpss entry rate, 2 times compression times and 4 times compression ratio can be processed, which can meet the general real-time processing requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN764
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