光接收芯片內(nèi)時(shí)鐘數(shù)據(jù)恢復(fù)電路的設(shè)計(jì)
發(fā)布時(shí)間：2018-09-12 18:40
【摘要】：光纖通訊具有容量大、抗干擾能力強(qiáng)、傳輸距離遠(yuǎn)、節(jié)能等優(yōu)點(diǎn),成為目前研究的熱門課題。在光纖通訊的過(guò)程中,需要時(shí)鐘數(shù)據(jù)恢復(fù)電路提取時(shí)鐘,并對(duì)數(shù)據(jù)進(jìn)行重定時(shí)以抑制抖動(dòng)。目前我國(guó)的主流光纖傳輸速率是2.5Gbps,隨著光纖傳輸?shù)乃俣群鸵笾鸩教嵘?10Gbps的光纖傳輸速率必將成為未來(lái)的主流。因此本論文的主要目標(biāo)是設(shè)計(jì)一款中心頻率為10Gbps的時(shí)鐘數(shù)據(jù)恢復(fù)(CDR)電路芯片。論文采用鎖相環(huán)為基礎(chǔ)的時(shí)鐘數(shù)據(jù)恢復(fù)電路結(jié)構(gòu),電路包括鑒頻器(FD)、鑒相器(PD)、低通濾波器(LPF)、電荷泵(CP)、壓控振蕩器(VCO)以及重定時(shí)模塊。為減少抖動(dòng)積累并產(chǎn)生高頻振蕩,采用低噪聲結(jié)構(gòu)的LC壓控振蕩器產(chǎn)生高頻時(shí)鐘信號(hào)。在電荷泵模塊設(shè)立參考電平,保證控制電壓的變化幅度限制在壓控振蕩器的線性區(qū)以內(nèi)。鑒頻器采用下降選頻的新型結(jié)構(gòu)以達(dá)到1.35GHz的超大范圍頻率捕捉,鑒相器采用前置D觸發(fā)器優(yōu)化過(guò)零點(diǎn),并使時(shí)鐘信號(hào)保持在數(shù)據(jù)位中間點(diǎn)采樣,為抖動(dòng)和不確定因素提供最大的裕度。鑒頻器和鑒相器可在頻率逼近后完成工作切換,縮短捕捉時(shí)間,提升了工作效率。通過(guò)調(diào)節(jié)環(huán)路參數(shù)使系統(tǒng)達(dá)到鎖定。輸入數(shù)據(jù)經(jīng)過(guò)提取后的時(shí)鐘重定時(shí),輸出抖動(dòng)大大降低。在Cadence下對(duì)時(shí)鐘數(shù)據(jù)恢復(fù)電路各個(gè)模塊及整體進(jìn)行了仿真分析,并給出了基于TSMC 0.18μm工藝的版圖繪制和后仿真。前仿真結(jié)果表明,本文所設(shè)計(jì)的時(shí)鐘數(shù)據(jù)恢復(fù)電路在3.3V的電源電壓下整體功耗為90mW,恢復(fù)出的10GHz時(shí)鐘相位噪聲為-87.5dBc/Hz,壓控振蕩器壓控增益為1.08GHz/V。在系統(tǒng)鎖定后,輸出時(shí)鐘的峰峰值抖動(dòng)為3ps,重定時(shí)后的數(shù)據(jù)輸出抖動(dòng)峰峰值為4.5ps。芯片版圖面積為300μm×500μm,后仿真結(jié)果表明,系統(tǒng)鎖定后輸出時(shí)鐘峰峰值抖動(dòng)為6ps,重定時(shí)后的數(shù)據(jù)輸出峰峰值抖動(dòng)為10ps,對(duì)比輸入數(shù)據(jù)15ps抖動(dòng),起到了很好的抖動(dòng)抑制效果。
[Abstract]:Optical fiber communication has many advantages, such as large capacity, strong anti-interference ability, long transmission distance, energy saving and so on. In the process of optical fiber communication, the clock data recovery circuit is needed to extract the clock and retiming the data to suppress the jitter. At present, the main fiber transmission rate in China is 2.5Gbps.With the speed and requirement of fiber transmission, the fiber transmission rate of 10Gbps will become the mainstream in the future. Therefore, the main goal of this thesis is to design a clock data recovery (CDR) chip with center frequency of 10Gbps. In this paper, a clock data recovery circuit based on PLL is used. The circuit includes a frequency discriminator, a (FD), phase discriminator, a (PD), low-pass filter, a (LPF), charge pump (CP), voltage-controlled oscillator (VCO) and a retiming module. In order to reduce jitter accumulation and generate high frequency oscillation, a low noise LC voltage-controlled oscillator is used to generate high frequency clock signal. The reference level is set up in the charge pump module to ensure that the range of the control voltage is limited to the linear range of the VCO. The frequency discriminator adopts a new structure of descending frequency selection to achieve the 1.35GHz super wide frequency capture. The phase detector uses a preposition D flip-flop to optimize the zero crossing point and to keep the clock signal sampling at the middle of the data bit. Provides maximum margin for jitter and uncertainty. Frequency discriminator and phase discriminator can complete the switching after frequency approaching, shorten the capture time and improve the working efficiency. The system is locked by adjusting the loop parameters. After the input data is extracted, the output jitter is greatly reduced when the clock is retimed. Each module and whole of clock data recovery circuit are simulated and analyzed in Cadence, and the layout drawing and post simulation based on TSMC 0.18 渭 m technology are given. The pre-simulation results show that the overall power consumption of the designed clock data recovery circuit is 90 MW at 3.3 V supply voltage, the recovered 10GHz clock phase noise is -87.5 dBc / Hz, and the voltage control gain of the VCO is 1.08 GHz / V. After the system is locked, the peak jitter of the output clock is 3 pss, and the peak value of the data output jitter after retiming is 4.5 ps. The chip layout area is 300 渭 m 脳 500 渭 m. The post-simulation results show that the peak jitter of the output clock peak is 6 pss after locking and the peak jitter of the data output peak after retiming is 10 ps.Compared with the 15ps jitter of input data, the jitter suppression effect is very good.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN929.11;TN402
本文編號(hào)：2239899
[Abstract]:Optical fiber communication has many advantages, such as large capacity, strong anti-interference ability, long transmission distance, energy saving and so on. In the process of optical fiber communication, the clock data recovery circuit is needed to extract the clock and retiming the data to suppress the jitter. At present, the main fiber transmission rate in China is 2.5Gbps.With the speed and requirement of fiber transmission, the fiber transmission rate of 10Gbps will become the mainstream in the future. Therefore, the main goal of this thesis is to design a clock data recovery (CDR) chip with center frequency of 10Gbps. In this paper, a clock data recovery circuit based on PLL is used. The circuit includes a frequency discriminator, a (FD), phase discriminator, a (PD), low-pass filter, a (LPF), charge pump (CP), voltage-controlled oscillator (VCO) and a retiming module. In order to reduce jitter accumulation and generate high frequency oscillation, a low noise LC voltage-controlled oscillator is used to generate high frequency clock signal. The reference level is set up in the charge pump module to ensure that the range of the control voltage is limited to the linear range of the VCO. The frequency discriminator adopts a new structure of descending frequency selection to achieve the 1.35GHz super wide frequency capture. The phase detector uses a preposition D flip-flop to optimize the zero crossing point and to keep the clock signal sampling at the middle of the data bit. Provides maximum margin for jitter and uncertainty. Frequency discriminator and phase discriminator can complete the switching after frequency approaching, shorten the capture time and improve the working efficiency. The system is locked by adjusting the loop parameters. After the input data is extracted, the output jitter is greatly reduced when the clock is retimed. Each module and whole of clock data recovery circuit are simulated and analyzed in Cadence, and the layout drawing and post simulation based on TSMC 0.18 渭 m technology are given. The pre-simulation results show that the overall power consumption of the designed clock data recovery circuit is 90 MW at 3.3 V supply voltage, the recovered 10GHz clock phase noise is -87.5 dBc / Hz, and the voltage control gain of the VCO is 1.08 GHz / V. After the system is locked, the peak jitter of the output clock is 3 pss, and the peak value of the data output jitter after retiming is 4.5 ps. The chip layout area is 300 渭 m 脳 500 渭 m. The post-simulation results show that the peak jitter of the output clock peak is 6 pss after locking and the peak jitter of the data output peak after retiming is 10 ps.Compared with the 15ps jitter of input data, the jitter suppression effect is very good.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN929.11;TN402
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，本文編號(hào)：2239899
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