應(yīng)用于高清數(shù)字視頻的低功耗流水線ADC的設(shè)計(jì)
發(fā)布時(shí)間：2018-09-11 10:48
【摘要】：現(xiàn)代電子系統(tǒng)的運(yùn)算處理部分幾乎全部實(shí)現(xiàn)了數(shù)字化,而在自然界中,信號(hào)基本上是以模擬的形式存在的,因而需要一個(gè)中間介質(zhì)把模擬信號(hào)轉(zhuǎn)化成數(shù)字信號(hào),這個(gè)介質(zhì)就是模數(shù)轉(zhuǎn)換器(ADC)。ADC作為數(shù)字與模擬的橋梁得到廣泛應(yīng)用,特別是在數(shù)字信號(hào)處理、雷達(dá)信號(hào)分析、醫(yī)療影像設(shè)備、多媒體設(shè)備等領(lǐng)域。本論文是以高清數(shù)字視頻顯示為應(yīng)用背景。高速高精度低功耗是ADC先進(jìn)技術(shù)的體現(xiàn)和未來(lái)的發(fā)展趨勢(shì)。高速高精度低功耗ADC芯片設(shè)計(jì)采用的結(jié)構(gòu)比較典型的有全并行結(jié)構(gòu)(flash)、流水線結(jié)構(gòu)(pipeline)、逐次逼近結(jié)構(gòu)(SAR)、delta-sigma型。由于pipeline ADC具有在精度、速度、面積以及功耗上折中的特點(diǎn),能夠很好地應(yīng)用于數(shù)字通信系統(tǒng)、高清視頻顯示系統(tǒng)等領(lǐng)域。隨著CMOS工藝的晶體管的特征尺寸不斷縮短,晶體管的精度速度功耗等性能指標(biāo)不斷提高,基于傳統(tǒng)的設(shè)計(jì)方法和結(jié)構(gòu)已不能滿足需求。因此,數(shù)字校正技術(shù)應(yīng)運(yùn)而生,可以大大提高ADC性能。本論文以高速高精度低功耗ADC為研究課題,通過(guò)對(duì)pipeline ADC的結(jié)構(gòu)以及性能指標(biāo)入手分析,在速度、精度、面積以及功耗折中的基礎(chǔ)上確定了pipeline ADC整體架構(gòu),并輔以片上數(shù)字校正以糾正設(shè)計(jì)中帶來(lái)的誤差,以消除誤差帶來(lái)的性能影響,并降低功耗和面積。本論文基于SMIC 55nm工藝完成了10bit 200M流水線ADC的電路模塊設(shè)計(jì),數(shù)字校正,前仿和版圖后仿。仿真結(jié)果顯示:在電源電壓1.2V,采樣頻率200MSPS,輸入頻率91MHz條件下,電路經(jīng)過(guò)校正后的有效位數(shù)達(dá)到9.86bit,同時(shí)模擬電路功耗只有68mW。
[Abstract]:In modern electronic systems, almost all of them are digitized. In nature, signals are basically in the form of analogue, so an intermediate medium is needed to convert analog signals into digital signals. This medium is called analog-to-digital converter (ADC), which is widely used as a bridge between digital and analog, especially in the fields of digital signal processing, radar signal analysis, medical imaging equipment, multimedia equipment and so on. This thesis is based on the application background of high-definition digital video display. High speed, high precision and low power consumption are the embodiment of ADC advanced technology and the development trend in the future. High speed, high precision and low power ADC chips are designed with typical (flash), pipelined (pipeline), approximation structure (SAR) delta-sigma type. Because of the tradeoff in precision, speed, area and power consumption, pipeline ADC can be used in digital communication system, high-definition video display system and other fields. As the characteristic size of transistors in CMOS process is shortened and the performance of transistors, such as precision, speed, power consumption and so on, is continuously improved, the traditional design methods and structures can not meet the requirements. Therefore, digital correction technology emerged as the times require, which can greatly improve the performance of ADC. In this paper, the high speed, high precision and low power ADC is used as the research subject. Through the analysis of the structure and performance of pipeline ADC, the overall framework of pipeline ADC is determined on the basis of speed, precision, area and power compromise. It is supplemented by on-chip digital correction to correct the errors in the design so as to eliminate the performance effects caused by the errors and to reduce the power consumption and area. In this paper, the circuit module design, digital correction, precopy and post-layout simulation of 10bit 200M pipeline ADC are completed based on SMIC 55nm process. The simulation results show that under the conditions of power supply voltage 1.2 V, sampling frequency 200mSPS and input frequency 91MHz, the corrected effective bit number of the circuit is 9.86 bit, and the power consumption of the analog circuit is only 68 MW.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792
本文編號(hào)：2236478
[Abstract]:In modern electronic systems, almost all of them are digitized. In nature, signals are basically in the form of analogue, so an intermediate medium is needed to convert analog signals into digital signals. This medium is called analog-to-digital converter (ADC), which is widely used as a bridge between digital and analog, especially in the fields of digital signal processing, radar signal analysis, medical imaging equipment, multimedia equipment and so on. This thesis is based on the application background of high-definition digital video display. High speed, high precision and low power consumption are the embodiment of ADC advanced technology and the development trend in the future. High speed, high precision and low power ADC chips are designed with typical (flash), pipelined (pipeline), approximation structure (SAR) delta-sigma type. Because of the tradeoff in precision, speed, area and power consumption, pipeline ADC can be used in digital communication system, high-definition video display system and other fields. As the characteristic size of transistors in CMOS process is shortened and the performance of transistors, such as precision, speed, power consumption and so on, is continuously improved, the traditional design methods and structures can not meet the requirements. Therefore, digital correction technology emerged as the times require, which can greatly improve the performance of ADC. In this paper, the high speed, high precision and low power ADC is used as the research subject. Through the analysis of the structure and performance of pipeline ADC, the overall framework of pipeline ADC is determined on the basis of speed, precision, area and power compromise. It is supplemented by on-chip digital correction to correct the errors in the design so as to eliminate the performance effects caused by the errors and to reduce the power consumption and area. In this paper, the circuit module design, digital correction, precopy and post-layout simulation of 10bit 200M pipeline ADC are completed based on SMIC 55nm process. The simulation results show that under the conditions of power supply voltage 1.2 V, sampling frequency 200mSPS and input frequency 91MHz, the corrected effective bit number of the circuit is 9.86 bit, and the power consumption of the analog circuit is only 68 MW.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792
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