一種混合信號型時分復(fù)用上電復(fù)位及模擬音量控制電路
發(fā)布時間：2018-09-10 08:43
【摘要】：為了滿足助聽器SoC高精度、低功耗應(yīng)用,提出一種基于8位逐次逼近模數(shù)轉(zhuǎn)換器的混合信號型時分復(fù)用上電復(fù)位及模擬音量控制電路。該電路利用逐次逼近模數(shù)轉(zhuǎn)換器輸出結(jié)束標(biāo)志信號作為時分信號,對電池電壓和模擬音量電壓進行交替檢測。數(shù)字邏輯電路可實現(xiàn)對上電、欠壓閾值以及延遲時間的靈活配置,同時也可進行信號處理以及產(chǎn)生上電復(fù)位和欠壓報警信號。電路采用SMIC 130nm 1P8M混合信號工藝實現(xiàn)。測試結(jié)果表明,在供電電壓1V時,電路能夠完成高精度的上電復(fù)位、欠壓報警和模擬音量檢測功能;輸入120 Hz正弦信號和15kHz時鐘頻率時,逐次逼近模數(shù)轉(zhuǎn)換器輸出信號最大信噪失真比為46.5dB,功耗僅有86μW。
[Abstract]:In order to meet the high precision and low power consumption of hearing aid SoC, a hybrid signal time division multiplexing (TDM) power reset and analog volume control circuit based on 8-bit successive approximation ADC is proposed. The circuit uses successive approximation A / D converter output signal as time division signal to detect battery voltage and analog volume voltage alternately. The digital logic circuit can realize the flexible configuration of power up, undervoltage threshold and delay time, at the same time, it can also process signals and generate reset and undervoltage alarm signals. The circuit is realized by SMIC 130nm 1P8M mixed signal technology. The test results show that when the supply voltage is 1 V, the circuit can perform the functions of high precision reset, undervoltage alarm and analog volume detection, and when the sinusoidal signal of 120 Hz and the clock frequency of 15kHz are input, The maximum signal-to-noise distortion ratio of the output signal is 46.5 dB, and the power consumption is only 86 渭 W.
【作者單位】： 廈門理工學(xué)院光電與通信工程學(xué)院;中國科學(xué)院微電子研究所;
【基金】：國家自然科學(xué)基金資助項目(61704143) 福建省中青年教師教育科研項目(JAT170428)
【分類號】：TN402
[Abstract]:In order to meet the high precision and low power consumption of hearing aid SoC, a hybrid signal time division multiplexing (TDM) power reset and analog volume control circuit based on 8-bit successive approximation ADC is proposed. The circuit uses successive approximation A / D converter output signal as time division signal to detect battery voltage and analog volume voltage alternately. The digital logic circuit can realize the flexible configuration of power up, undervoltage threshold and delay time, at the same time, it can also process signals and generate reset and undervoltage alarm signals. The circuit is realized by SMIC 130nm 1P8M mixed signal technology. The test results show that when the supply voltage is 1 V, the circuit can perform the functions of high precision reset, undervoltage alarm and analog volume detection, and when the sinusoidal signal of 120 Hz and the clock frequency of 15kHz are input, The maximum signal-to-noise distortion ratio of the output signal is 46.5 dB, and the power consumption is only 86 渭 W.
【作者單位】： 廈門理工學(xué)院光電與通信工程學(xué)院;中國科學(xué)院微電子研究所;
【基金】：國家自然科學(xué)基金資助項目(61704143) 福建省中青年教師教育科研項目(JAT170428)
【分類號】：TN402
【相似文獻(xiàn)】
相關(guān)期刊論文 前10條
1 高明倫,張紅莉,徐諾;一種基于比較器的新型片內(nèi)上電復(fù)位電路的實現(xiàn)[J];中國集成電路;2004年08期
2 魯斌;胡永華;王曉蕾;;基于系統(tǒng)監(jiān)控的片內(nèi)上電復(fù)位電路的實現(xiàn)[J];中國集成電路;2006年02期
3 張晉;蔣林;曾澤滄;;一種新型的片內(nèi)上電復(fù)位電路的設(shè)計[J];西安郵電學(xué)院學(xué)報;2009年05期
4 王漢祥;李富華;謝衛(wèi)國;;一種高可靠性上電復(fù)位芯片的設(shè)計[J];現(xiàn)代電子技術(shù);2009年02期
5 李昌紅;劉超;于臻;魏濤;;一種新型低功耗上電復(fù)位電路設(shè)計[J];物聯(lián)網(wǎng)技術(shù);2011年07期
6 彭偉娣;張文杰;謝亮;金湘亮;;一種嵌入式上電復(fù)位電路的設(shè)計與芯片實現(xiàn)[J];固體電子學(xué)研究與進展;2013年02期
7 王小曼;原義棟;張海峰;;一種低功耗高可靠上電復(fù)位電路的設(shè)計[J];微電子學(xué);2011年05期
8 單偉偉;周W，
本文編號：2233947
本文鏈接：http://lk138.cn/kejilunwen/dianzigongchenglunwen/2233947.html
最近更新
教材專著
