一種混合信號(hào)型時(shí)分復(fù)用上電復(fù)位及模擬音量控制電路
發(fā)布時(shí)間：2018-09-10 08:43
【摘要】：為了滿足助聽器SoC高精度、低功耗應(yīng)用,提出一種基于8位逐次逼近模數(shù)轉(zhuǎn)換器的混合信號(hào)型時(shí)分復(fù)用上電復(fù)位及模擬音量控制電路。該電路利用逐次逼近模數(shù)轉(zhuǎn)換器輸出結(jié)束標(biāo)志信號(hào)作為時(shí)分信號(hào),對(duì)電池電壓和模擬音量電壓進(jìn)行交替檢測(cè)。數(shù)字邏輯電路可實(shí)現(xiàn)對(duì)上電、欠壓閾值以及延遲時(shí)間的靈活配置,同時(shí)也可進(jìn)行信號(hào)處理以及產(chǎn)生上電復(fù)位和欠壓報(bào)警信號(hào)。電路采用SMIC 130nm 1P8M混合信號(hào)工藝實(shí)現(xiàn)。測(cè)試結(jié)果表明,在供電電壓1V時(shí),電路能夠完成高精度的上電復(fù)位、欠壓報(bào)警和模擬音量檢測(cè)功能;輸入120 Hz正弦信號(hào)和15kHz時(shí)鐘頻率時(shí),逐次逼近模數(shù)轉(zhuǎn)換器輸出信號(hào)最大信噪失真比為46.5dB,功耗僅有86μW。
[Abstract]:In order to meet the high precision and low power consumption of hearing aid SoC, a hybrid signal time division multiplexing (TDM) power reset and analog volume control circuit based on 8-bit successive approximation ADC is proposed. The circuit uses successive approximation A / D converter output signal as time division signal to detect battery voltage and analog volume voltage alternately. The digital logic circuit can realize the flexible configuration of power up, undervoltage threshold and delay time, at the same time, it can also process signals and generate reset and undervoltage alarm signals. The circuit is realized by SMIC 130nm 1P8M mixed signal technology. The test results show that when the supply voltage is 1 V, the circuit can perform the functions of high precision reset, undervoltage alarm and analog volume detection, and when the sinusoidal signal of 120 Hz and the clock frequency of 15kHz are input, The maximum signal-to-noise distortion ratio of the output signal is 46.5 dB, and the power consumption is only 86 渭 W.
【作者單位】： 廈門理工學(xué)院光電與通信工程學(xué)院;中國(guó)科學(xué)院微電子研究所;
【基金】：國(guó)家自然科學(xué)基金資助項(xiàng)目(61704143) 福建省中青年教師教育科研項(xiàng)目(JAT170428)
【分類號(hào)】：TN402
[Abstract]:In order to meet the high precision and low power consumption of hearing aid SoC, a hybrid signal time division multiplexing (TDM) power reset and analog volume control circuit based on 8-bit successive approximation ADC is proposed. The circuit uses successive approximation A / D converter output signal as time division signal to detect battery voltage and analog volume voltage alternately. The digital logic circuit can realize the flexible configuration of power up, undervoltage threshold and delay time, at the same time, it can also process signals and generate reset and undervoltage alarm signals. The circuit is realized by SMIC 130nm 1P8M mixed signal technology. The test results show that when the supply voltage is 1 V, the circuit can perform the functions of high precision reset, undervoltage alarm and analog volume detection, and when the sinusoidal signal of 120 Hz and the clock frequency of 15kHz are input, The maximum signal-to-noise distortion ratio of the output signal is 46.5 dB, and the power consumption is only 86 渭 W.
【作者單位】： 廈門理工學(xué)院光電與通信工程學(xué)院;中國(guó)科學(xué)院微電子研究所;
【基金】：國(guó)家自然科學(xué)基金資助項(xiàng)目(61704143) 福建省中青年教師教育科研項(xiàng)目(JAT170428)
【分類號(hào)】：TN402
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