頻譜自適應通信波形FPGA實現(xiàn)關鍵技術(shù)研究
發(fā)布時間：2018-09-05 13:45
【摘要】：隨著科技的迅猛發(fā)展和人們對無線通信的極大需求,無線通信技術(shù)取得了突飛猛進的發(fā)展。相比飛速發(fā)展的陸地通信,航空通信的發(fā)展還處于比較落后的狀態(tài),亟需提高航空通信的速率、可靠性和抗干擾能力。本文基于非連續(xù)正交頻分復用(Non-Contiguous Orthogonal Frequency Division Multiplexing,NC-OFDM)技術(shù),利用頻譜感知結(jié)果,在FPGA(Field Programmable Gate Array)中實現(xiàn)頻譜自適應的通信波形生成和接收的關鍵技術(shù)。論文第一章簡要介紹了本文的研究意義和多載波技術(shù),在介紹OFDM(Orthogonal Frequency Division Multiplexing)技術(shù)的基礎上,分析了將NC-OFDM應用于頻譜自適應系統(tǒng)的可能性。論文第二章對鏈路模型和系統(tǒng)開發(fā)平臺進行簡要介紹,首先從功能和原理兩方面對鏈路中的各個模塊進行了描述。接下來介紹了開發(fā)平臺中的基帶板和射頻板。基帶板中包含2個TI 2C6670 DSP(Digital Signal Processor)和2兩塊Xilinx FPGA,其中DSP主要完成編譯碼、交織和加擾,FPGA則實現(xiàn)收發(fā)機的數(shù)字基帶的信號處理。射頻板將基帶數(shù)據(jù)加載到高頻載波上,同時對收發(fā)信號進行濾波處理。論文第三章對頻譜自適應多載波波形的收發(fā)關鍵技術(shù)進行了分析,詳細描述了這些技術(shù)的FPGA實現(xiàn)。在波形發(fā)送關鍵技術(shù)實現(xiàn)部分,主要描述數(shù)據(jù)映射、CCSK(Cyclic Code Shift Keying)調(diào)制、導引符號生成、OFDM調(diào)制、同步序列生成、帶外抑制和組幀、PAPR(Peak to Average Power Ratio)抑制的FPGA實現(xiàn);在波形接收關鍵技術(shù)實現(xiàn)部分,描述了同步、解幀和干擾抑制、OFDM解調(diào)、信道估計、16QAM(Quadrature Amptitude Modulation)軟解調(diào)和CCSK硬解調(diào)的FPGA實現(xiàn)。論文第四章介紹平臺開發(fā)中使用的SRIO(Serial Rapid Input/Output)和CPRI(Common Public Radio Interface)接口協(xié)議,同時給出SRIO接口和CPRI接口的實現(xiàn)方式。SRIO接口的實現(xiàn)采用了Xilinx的rio_wrapper解決方案,通過實現(xiàn)SRIO邏輯層的SWRITE和DOORBELL兩種數(shù)據(jù)傳輸模式,實現(xiàn)SRIO接口的數(shù)據(jù)傳輸。CPRI接口實現(xiàn)則采用CPRI核,根據(jù)鏈路速率和接口速率,采用向下兼容映射方式把要發(fā)送的基帶I/Q(In-phase/Quadranture)數(shù)據(jù)映射到CPRI接口的基本幀中,同時把接收基本幀中的數(shù)據(jù)反映射為基帶數(shù)據(jù),實現(xiàn)基帶板與射頻板的通信。第五章對關鍵模塊FPGA實現(xiàn)和整體鏈路進行性能測試。首先對頻偏估計模塊進行了性能測試,測試數(shù)據(jù)表明:頻偏估計模塊在系統(tǒng)工作點能夠非常精確的估計出頻偏值,滿足大頻偏的巡航場景下的頻偏估計要求。通過PAPR模塊的測試,表明PAPR抑制模塊能夠有效的抑制發(fā)送信號PAPR值,能夠滿足系統(tǒng)PAPR要求。進一步,利用信道仿真器模擬高斯信道和巡航信道,測試兩種信道下的性能;同時測試了添加20%的部分帶干擾下的鏈路性能。通過與仿真結(jié)果比較,驗證實現(xiàn)的正確性。最后聯(lián)合DSP實現(xiàn)的turbo編譯碼進行全鏈路的測試,結(jié)果表明系統(tǒng)具有良好的傳輸性能,且滿足滿足航空通信的需求。第六章為全文總結(jié),并提出了工作展望與方向。
[Abstract]:With the rapid development of science and technology and people's great demand for wireless communication, wireless communication technology has made rapid development. Compared with the rapid development of land communication, the development of aviation communication is still relatively backward. It is urgent to improve the rate, reliability and anti-jamming ability of aviation communication. Based on discontinuous orthogonal Frequency Division Multiplexing (Non-Contiguous Orthogonal Frequency Division Multiplexing,NC-OFDM) and using spectrum sensing results, this paper presents the key techniques for generating and receiving spectrum adaptive communication waveforms in FPGA (Field Programmable Gate Array). In the first chapter, the significance of this paper and the multicarrier technology are briefly introduced. On the basis of the introduction of OFDM (Orthogonal Frequency Division Multiplexing) technology, the possibility of applying NC-OFDM to the spectrum adaptive system is analyzed. In the second chapter, the link model and the system development platform are briefly introduced. Firstly, each module in the link is described from the aspects of function and principle. Then the base band board and radio frequency board in the development platform are introduced. The baseband board consists of two TI 2C6670 DSP (Digital Signal Processor) and two Xilinx FPGA, in which the DSP is mainly used to code and decode, and the interleaved and scrambled FPGA is used to process the digital baseband signal of the transceiver. The RF board loads the baseband data onto the high frequency carrier and filters the transceiver signal. In the third chapter, the key technologies of spectrum adaptive multicarrier waveform are analyzed, and the FPGA implementation of these technologies is described in detail. In the key technology of waveform transmission, we mainly describe the FPGA implementation of data mapping CCSK (Cyclic Code Shift Keying) modulation, pilot symbol generation, synchronization sequence generation, out-of-band suppression and framing PAPR (Peak to Average Power Ratio) suppression. In the key technology of waveform receiving, the FPGA implementation of synchronization, unframing and interference suppression (Quadrature Amptitude Modulation) demodulation, channel estimation 16QAM (Quadrature Amptitude Modulation) soft demodulation and CCSK hard demodulation are described. Chapter 4 introduces the SRIO (Serial Rapid Input/Output) and CPRI (Common Public Radio Interface) interface protocol used in the platform development. At the same time, the realization of SRIO interface and CPRI interface is implemented with the rio_wrapper solution of Xilinx. Through the realization of SWRITE and DOORBELL data transmission mode in SRIO logic layer, the data transmission. CPRI interface of SRIO interface is realized by CPRI core, according to link rate and interface rate. The baseband I / Q (In-phase/Quadranture) data to be transmitted is mapped to the basic frame of the CPRI interface by the way of downward compatible mapping. At the same time, the data in the received basic frame is reflected as baseband data, and the communication between the baseband board and the RF board is realized. In the fifth chapter, we test the performance of the key module FPGA and the whole link. First, the performance of the frequency offset estimation module is tested. The test data show that the frequency offset estimation module can estimate the frequency offset very accurately at the operating point of the system, which can meet the requirements of frequency offset estimation in the cruising scene with large frequency offset. The test of the PAPR module shows that the PAPR suppression module can effectively suppress the PAPR value of the transmitted signal and meet the requirements of the system PAPR. Furthermore, the channel simulator is used to simulate Gao Si channel and cruise channel to test the performance of the two channels, and the link performance with 20% partial interference is tested. The correctness of the implementation is verified by comparing with the simulation results. Finally, the turbo code and decode implemented by DSP is used to test the whole link. The results show that the system has good transmission performance and meets the requirements of aviation communication. The sixth chapter is the summary of the full text, and puts forward the work prospect and direction.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN929.53;TN791
本文編號：2224451
[Abstract]:With the rapid development of science and technology and people's great demand for wireless communication, wireless communication technology has made rapid development. Compared with the rapid development of land communication, the development of aviation communication is still relatively backward. It is urgent to improve the rate, reliability and anti-jamming ability of aviation communication. Based on discontinuous orthogonal Frequency Division Multiplexing (Non-Contiguous Orthogonal Frequency Division Multiplexing,NC-OFDM) and using spectrum sensing results, this paper presents the key techniques for generating and receiving spectrum adaptive communication waveforms in FPGA (Field Programmable Gate Array). In the first chapter, the significance of this paper and the multicarrier technology are briefly introduced. On the basis of the introduction of OFDM (Orthogonal Frequency Division Multiplexing) technology, the possibility of applying NC-OFDM to the spectrum adaptive system is analyzed. In the second chapter, the link model and the system development platform are briefly introduced. Firstly, each module in the link is described from the aspects of function and principle. Then the base band board and radio frequency board in the development platform are introduced. The baseband board consists of two TI 2C6670 DSP (Digital Signal Processor) and two Xilinx FPGA, in which the DSP is mainly used to code and decode, and the interleaved and scrambled FPGA is used to process the digital baseband signal of the transceiver. The RF board loads the baseband data onto the high frequency carrier and filters the transceiver signal. In the third chapter, the key technologies of spectrum adaptive multicarrier waveform are analyzed, and the FPGA implementation of these technologies is described in detail. In the key technology of waveform transmission, we mainly describe the FPGA implementation of data mapping CCSK (Cyclic Code Shift Keying) modulation, pilot symbol generation, synchronization sequence generation, out-of-band suppression and framing PAPR (Peak to Average Power Ratio) suppression. In the key technology of waveform receiving, the FPGA implementation of synchronization, unframing and interference suppression (Quadrature Amptitude Modulation) demodulation, channel estimation 16QAM (Quadrature Amptitude Modulation) soft demodulation and CCSK hard demodulation are described. Chapter 4 introduces the SRIO (Serial Rapid Input/Output) and CPRI (Common Public Radio Interface) interface protocol used in the platform development. At the same time, the realization of SRIO interface and CPRI interface is implemented with the rio_wrapper solution of Xilinx. Through the realization of SWRITE and DOORBELL data transmission mode in SRIO logic layer, the data transmission. CPRI interface of SRIO interface is realized by CPRI core, according to link rate and interface rate. The baseband I / Q (In-phase/Quadranture) data to be transmitted is mapped to the basic frame of the CPRI interface by the way of downward compatible mapping. At the same time, the data in the received basic frame is reflected as baseband data, and the communication between the baseband board and the RF board is realized. In the fifth chapter, we test the performance of the key module FPGA and the whole link. First, the performance of the frequency offset estimation module is tested. The test data show that the frequency offset estimation module can estimate the frequency offset very accurately at the operating point of the system, which can meet the requirements of frequency offset estimation in the cruising scene with large frequency offset. The test of the PAPR module shows that the PAPR suppression module can effectively suppress the PAPR value of the transmitted signal and meet the requirements of the system PAPR. Furthermore, the channel simulator is used to simulate Gao Si channel and cruise channel to test the performance of the two channels, and the link performance with 20% partial interference is tested. The correctness of the implementation is verified by comparing with the simulation results. Finally, the turbo code and decode implemented by DSP is used to test the whole link. The results show that the system has good transmission performance and meets the requirements of aviation communication. The sixth chapter is the summary of the full text, and puts forward the work prospect and direction.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN929.53;TN791
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