本文選題：三維可重構(gòu)陣列 + 自主容錯(cuò)　； 參考：《南京航空航天大學(xué)》2013年碩士論文

【摘要】：隨著集成電路技術(shù)的飛速發(fā)展，數(shù)字電子系統(tǒng)的集成度大幅提高，在生命周期內(nèi)發(fā)生故障的概率也隨之增加�？芍貥�(gòu)硬件具有功能靈活、開發(fā)周期短等優(yōu)點(diǎn)，，已廣泛應(yīng)用于航空航天等領(lǐng)域的關(guān)鍵電子系統(tǒng)中，由于工作環(huán)境惡劣且人工難以維護(hù)，對(duì)可重構(gòu)硬件的可靠性要求更高。因此，以提高可靠性為目標(biāo)的可重構(gòu)硬件容錯(cuò)設(shè)計(jì)具有重要意義。 可重構(gòu)硬件的自主容錯(cuò)是指在不需要外部控制器進(jìn)行控制的情況下，實(shí)現(xiàn)故障自主修復(fù)。目前二維可重構(gòu)硬件的自主容錯(cuò)方法中，重布線機(jī)制不易實(shí)現(xiàn)，特別是在一些大規(guī)模系統(tǒng)中，布線擁塞和延遲現(xiàn)象嚴(yán)重，導(dǎo)致容錯(cuò)時(shí)間開銷大，容錯(cuò)能力不高。三維陣列結(jié)構(gòu)可顯著減少布線長(zhǎng)度，提高布線過程布通率和布線機(jī)制靈活性，給可重構(gòu)硬件的容錯(cuò)方法設(shè)計(jì)提供了新思路。 本文利用三維陣列結(jié)構(gòu)在布線靈活性方面的優(yōu)勢(shì)，對(duì)三維可重構(gòu)陣列的自主容錯(cuò)方法進(jìn)行研究，論文的主要研究工作如下： （1）設(shè)計(jì)了一種三維結(jié)構(gòu)的可重構(gòu)陣列，可有效改善二維可重構(gòu)硬件重布線機(jī)制不靈活，容錯(cuò)控制復(fù)雜度隨陣列規(guī)模增大而增加，難以大規(guī)模實(shí)現(xiàn)等問題，并且在此結(jié)構(gòu)上對(duì)功能細(xì)胞和三維開關(guān)塊進(jìn)行了容錯(cuò)設(shè)計(jì)，使可重構(gòu)陣列具有自主容錯(cuò)能力。三維開關(guān)塊用于實(shí)現(xiàn)功能細(xì)胞在六個(gè)方向上的信息傳遞，提高了布線機(jī)制靈活性的同時(shí)，還具有在線自測(cè)試與自修復(fù)能力；功能細(xì)胞內(nèi)部設(shè)有容錯(cuò)控制模塊，可實(shí)現(xiàn)細(xì)胞的在線自主容錯(cuò)，減少容錯(cuò)控制復(fù)雜度。 （2）對(duì)可重構(gòu)硬件的自主容錯(cuò)方法進(jìn)行了研究，采用在線分布式輸入測(cè)試向量的方法，能夠?qū)收线M(jìn)行精確定位，測(cè)試速度快且測(cè)試機(jī)制實(shí)現(xiàn)簡(jiǎn)單；容錯(cuò)過程中，采用分層修復(fù)方法，根據(jù)診斷結(jié)果執(zhí)行相應(yīng)修復(fù)機(jī)制，對(duì)細(xì)胞內(nèi)底層冗余資源和可重構(gòu)陣列空閑互連資源進(jìn)行合理利用，充分提高資源利用率和容錯(cuò)速率。 （3）本文最后以四位并行乘法器和四位加法/減法器為例，在三維可重構(gòu)陣列上實(shí)現(xiàn)功能映射，對(duì)其進(jìn)行仿真和下板測(cè)試，驗(yàn)證了可重構(gòu)陣列的邏輯功能與自主容錯(cuò)能力，并且在容錯(cuò)能力、硬件資源開銷和容錯(cuò)時(shí)間開銷三方面與其他典型可重構(gòu)硬件容錯(cuò)技術(shù)進(jìn)行了分析對(duì)比，說明本文提出的三維可重構(gòu)陣列自主容錯(cuò)方法具有容錯(cuò)能力高，硬件資源開銷小和容錯(cuò)速度快等優(yōu)勢(shì)。
[Abstract]:With the rapid development of integrated circuit technology, the integration of digital electronic system has been greatly improved, and the probability of failure in the life cycle has also increased. Reconfigurable hardware has the advantages of flexible function and short development cycle. It has been widely used in the key electronic systems in aerospace and other fields. Because of the harsh working environment and difficult to maintain, the reliability of reconfigurable hardware is higher than that of reconfigurable hardware. Therefore, it is of great significance to improve the reliability of reconfigurable hardware fault-tolerant design. The autonomous fault tolerance of reconfigurable hardware refers to the implementation of autonomous fault recovery without the need of external controller control. At present, the rerouting mechanism is not easy to implement in two-dimensional reconfigurable hardware, especially in some large-scale systems, the routing congestion and delay are serious, resulting in a large amount of fault-tolerant time overhead and low fault-tolerant ability. Three-dimensional array structure can significantly reduce routing length, improve routing process routing rate and routing mechanism flexibility, and provide a new idea for fault tolerant design of reconfigurable hardware. This paper makes use of the advantages of three-dimensional array structure in routing flexibility. The main work of this paper is as follows: 1) A reconfigurable array with 3D structure is designed, which can effectively improve the rerouting mechanism of two-dimensional reconfigurable hardware. The complexity of fault-tolerant control increases with the increase of array size, which is difficult to implement on a large scale. In this structure, fault-tolerant design for functional cells and 3D switching blocks is carried out to make the reconfigurable array have autonomous fault-tolerant capability. Three-dimensional switch block is used to realize information transmission in six directions of functional cells, which improves the flexibility of routing mechanism, and also has the ability of on-line self-testing and self-repairing, and has fault-tolerant control module inside functional cells. It can realize the on-line autonomous fault-tolerant of cells and reduce the complexity of fault-tolerant control. (X2) the autonomous fault-tolerant method of reconfigurable hardware is studied. The method of on-line distributed input test vector can accurately locate the fault. In the process of fault tolerance, the hierarchical repair method is used to carry out the corresponding repair mechanism according to the diagnosis results, and the redundant resources in the bottom layer of the cell and the idle interconnection resources of the reconfigurable array are reasonably utilized. Finally, taking four bit parallel multiplier and four bit addition / subtraction as examples, we implement functional mapping on 3D reconfigurable array, simulate it and test it on the bottom board. The logic function and autonomous fault-tolerant ability of reconfigurable array are verified and compared with other typical reconfigurable hardware fault-tolerant techniques in three aspects: fault-tolerant capability, hardware resource overhead and fault-tolerant time cost. It is shown that the autonomous fault-tolerant method of 3D reconfigurable array presented in this paper has the advantages of high fault-tolerant capability, low cost of hardware resources and fast fault-tolerant speed.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP302.8

【參考文獻(xiàn)】

相關(guān)期刊論文 前7條

1 徐建軍;譚慶平;熊蔭喬;譚蘭芳;李建立;;面向瞬態(tài)故障的軟件容錯(cuò)技術(shù)[J];計(jì)算機(jī)工程與科學(xué);2011年11期

2 袁鵬;王友仁;張砦;;可重構(gòu)電子系統(tǒng)芯片級(jí)在線自主容錯(cuò)方法研究[J];計(jì)算機(jī)應(yīng)用研究;2012年06期

3 孫川;王友仁;張砦;張宇;;可重構(gòu)陣列自主容錯(cuò)方法[J];信息與控制;2010年05期

4 郝國(guó)鋒;王友仁;張砦;孫川;;可重構(gòu)硬件內(nèi)建自測(cè)試與容錯(cuò)機(jī)制研究[J];儀器儀表學(xué)報(bào);2011年04期

5 邊華;陳斌;;軟件容錯(cuò)技術(shù)與可靠性評(píng)估方法[J];中國(guó)化工裝備;2006年04期

6 黃影;張春元;劉東;;SRAM型FPGA的抗SEU方法研究[J];中國(guó)空間科學(xué)技術(shù);2007年04期

7 龔健;楊孟飛;文亮;;面向進(jìn)化容錯(cuò)的FPGA故障模型研究[J];中國(guó)空間科學(xué)技術(shù);2009年03期

本文編號(hào)：2001523