本文關(guān)鍵詞： 同步信號 FPGA 直接數(shù)字頻率合成 UART　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：FPGA(Field Programmable Gate Array)器件的應(yīng)用是繼單片機(jī)之后,當(dāng)今嵌入式系統(tǒng)開發(fā)的關(guān)鍵技術(shù)之一,無論在高校還是企業(yè)都得到了廣泛的應(yīng)用。直接數(shù)字頻率合成(DDS,Direct Digital Synthesizer)技術(shù)是從信號相位概念出發(fā),以高速數(shù)字器件為基礎(chǔ),直接合成所需波形的一種全數(shù)字頻率合成技術(shù),相對于傳統(tǒng)的模擬頻率合成技術(shù),具有成本低廉,性能穩(wěn)定,功能集成度高以及產(chǎn)品體積小等一系列優(yōu)點(diǎn)。本文以FPGA為硬件基礎(chǔ),結(jié)合DDS技術(shù)作為理論支撐,設(shè)計(jì)了一款同步信號發(fā)生器,其功能是產(chǎn)生兩路頻率可實(shí)時調(diào)整,且分辨率在0.001Hz以下的方波信號,分別作為視頻信號的行同步信號和場同步信號,最終運(yùn)用在視頻還原項(xiàng)目中。本文的主要工作如下:1.對串行異步通信進(jìn)行了研究。根據(jù)項(xiàng)目的實(shí)際需求,需要通過計(jì)算機(jī)來控制FPGA輸出兩路同步信號,考慮到串行通信具有成本低,易實(shí)現(xiàn)的特點(diǎn),因此采用通用異步收發(fā)傳輸器(UART,Universal Asynchronous Receiver/Transmitter)作為計(jì)算機(jī)與FPGA的通信接口。本文主要對該通信方式的數(shù)據(jù)格式、波特率以及數(shù)據(jù)采樣等特性進(jìn)行了研究,并在FPGA上設(shè)計(jì)實(shí)現(xiàn)了這種通信方式。2.對DDS技術(shù)進(jìn)行了研究。計(jì)算機(jī)將目標(biāo)信號的頻率值通過串口傳輸?shù)紽PGA內(nèi)部后,以DDS的方式合成信號,因此本文對DDS的技術(shù)原理及實(shí)現(xiàn)方式進(jìn)行了研究,并在FPGA內(nèi)部搭建了以DDS為基礎(chǔ)的模塊。由于同步信號發(fā)生器最終產(chǎn)生的是方波信號,并不需要產(chǎn)生正弦波和三角波,本文對DDS的ROM模塊進(jìn)行了簡化和修改,使其更加適合項(xiàng)目的需求。3.對所有模塊進(jìn)行綜合實(shí)現(xiàn)和仿真。模塊代碼完成之后,需要用綜合工具進(jìn)行由代碼轉(zhuǎn)換為實(shí)際電路的工作。本文采用Xilinx公司自帶的綜合工具ISE對模塊進(jìn)行編譯、綜合和布局布線,之后將程序燒入FPGA內(nèi)部,用示波器對波形進(jìn)行觀察。發(fā)現(xiàn)問題之后,通過不斷對程序進(jìn)行仿真與綜合,以及對輸出波形的直觀觀察查找問題,解決問題。4.完成最終電路板和上位機(jī)程序。波形正確之后,完成電路板的焊接工作,最后由于項(xiàng)目需求,即需要用計(jì)算機(jī)輸入頻率值,本文通過對串口調(diào)試程序源碼進(jìn)行更改,在計(jì)算機(jī)上實(shí)現(xiàn)上位機(jī)程序,可以順利的與FPGA之間進(jìn)行頻率信息的傳輸。
[Abstract]:The application of FPGA(Field Programmable Gate Arraydevice is one of the key technologies in the development of embedded system after the single chip microcomputer, which is widely used in universities and enterprises. Direct Digital Frequency Synthesis (DDS) Digital Synthesis (DDS) technology is based on the concept of signal phase. Based on high-speed digital devices, an all-digital frequency synthesizer which directly synthesizes the required waveforms, compared with the traditional analog frequency synthesis technology, has the advantages of low cost and stable performance. Based on FPGA and DDS technology, a synchronous signal generator is designed, whose function is to generate two channels of frequency that can be adjusted in real time. A square wave signal with a resolution of less than 0.001Hz is used as a line synchronization signal and a field synchronization signal, respectively. The main work of this paper is as follows: 1. The serial asynchronous communication is studied. According to the actual requirements of the project, we need to control the FPGA to output two synchronous signals through the computer. Considering the low cost and easy realization of serial communication, UART Universal Asynchronous receiver / Transmitter is used as the communication interface between computer and FPGA. The characteristics of baud rate and data sampling are studied, and this communication mode is designed and implemented on FPGA. The DDS technology is studied. The frequency value of the target signal is transmitted to the FPGA through the serial port by computer. In this paper, the technical principle and implementation of DDS are studied, and a module based on DDS is built in FPGA. Because the synchronous signal generator produces square wave signal, There is no need to generate sine wave and triangle wave. This paper simplifies and modifies the ROM module of DDS to make it more suitable for the requirements of the project .3.All the modules are implemented and simulated synthetically. After the completion of the module code, It is necessary to use synthesis tool to convert code to actual circuit. In this paper, the module is compiled, synthesized and wired by ISE, which is a comprehensive tool of Xilinx Company, and then the program is burned into FPGA. Using oscilloscope to observe the waveform. After discovering the problem, we can solve the problem by constantly emulating and synthesizing the program, and by observing and finding the output waveform directly. Finally, the final circuit board and upper computer program are completed. After the waveform is correct, To complete the welding of the circuit board, because of the requirement of the project, that is, to input the frequency value with the computer, this paper changes the source code of the serial port debugging program, and realizes the upper computer program on the computer. The frequency information can be transmitted smoothly with FPGA.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TM935

【相似文獻(xiàn)】

相關(guān)期刊論文 前3條

1 朱偉,沈紅光;采用EPLD設(shè)計(jì)視頻同步信號發(fā)生器的方法[J];航空電子技術(shù);1999年03期

2 魏建峰;王濤;張瑩;原芳;;基于CPLD的火控系統(tǒng)CAN總線同步信號發(fā)生器的設(shè)計(jì)[J];彈箭與制導(dǎo)學(xué)報(bào);2008年06期

3 ;[J];;年期

相關(guān)碩士學(xué)位論文 前2條

1 文羽航;基于FPGA的同步信號發(fā)生器設(shè)計(jì)[D];西安電子科技大學(xué);2015年

2 張?jiān)掠?視頻信息截獲平臺同步技術(shù)研究與實(shí)現(xiàn)[D];北京郵電大學(xué);2011年

，

本文編號：1535661